Abstract: A configuration is adopted including an NchMOS transistor (1) equipped with an insulating isolation layer (4) providing insulation and isolation using an SOI structure, and a capacitor formed using an insulating film, with a silicon substrate (B) being made thin and substrate capacitance being reduced. The NchMOS transistor (1) is equipped with insulating isolation regions (5a, 5b) that are perfectly depleted or partially depleted in a manner close to being perfectly depleted. An electrode (6) connected to a gate electrode (G) of the NchMOS transistor (1) and an impurity diffusion layer (7) are connected via a capacitor (2). A source electrode (S) is connected to a power supply terminal (3 a), a gate electrode (G) is connected to an internal signal line (S 1), and a drain electrode (D) is connected to an internal signal line (S2). Substrate bias voltage is then controlled using capacitor coupling when the NchMOS transistor (1) is turned on/off.

Abstract: Magnetic multilayer structures, such as magnetic or magnetoresistive tunnel junctions (MTJs) and spin valves, having one or more spin diffusion layers to diffuse the electron spins outside the MTJ or spin valve structure to reduce the spin transfer switching current for switching the free layer.

Abstract: The semiconductor device in which reading and writing of data can be accurately performed by preventing malfunction even when a selection of address delays. The semiconductor device has three factors of a data holding unit, a precharge unit and a delay unit. The data holding unit includes a plurality of memory cells. The precharge unit includes a precharge potential line, a precharge signal line and a plurality of switches. The delay unit includes a plurality of transistors. In addition, it has one or both of an address selecting unit having a column-decoder and a row-decoder and a display unit having a plurality of pixels, as well as the three factors.

Abstract: A nonvolatile semiconductor memory includes: a device region and a device isolating region, which have a pattern with a striped form that extends in a first direction, and are alternately and sequentially disposed at a first pitch in a second direction that is perpendicular to the first direction; and a contact made of a first conductive material, which is connected to the device region and disposed at the first pitch in the second direction. On a cross section of the second direction, the bottom width of the contact is longer than the top width of the contact, and the bottom width is longer than the width of the device region.

Abstract: An optical semiconductor device (A1) includes a light reflector (5) and an optical semiconductor chip (3). The reflector (5) includes two first reflecting surfaces (50a) spaced from each other in direction x, and two second reflecting surfaces (50b) spaced from each other in direction y. The chip (3) includes a rectangular upper surface and a rectangular lower surface spaced from each other in direction z perpendicular to both of the directions x and y. The chip (3) further includes at least one light-emitting surface (31) extending between the upper and the lower surfaces. The light-emitting surface (31) faces a corresponding one of the second reflecting surfaces (50b). The light-emitting surface (31) is non-parallel to the corresponding second reflecting surfaces (50b) as viewed in parallel to the direction z.

Abstract: A semiconductor memory device capable of reducing power consumption by employing a DLL drive controller. The semiconductor memory device includes: an idle state detector for detecting an idle state that all banks are precharged; a delay locked loop (DLL) for synchronizing an internal clock with an external clock; and a DLL drive controller for controlling the delay locked loop in response to an idle state detection signal outputted from the idle state detector and a delay locked signal outputted from the DLL.

Abstract: A NOR flash memory device and related programming method are disclosed. The programming method includes programming data in a memory cell and, during a program verification operation, controlling the supply of current from a sense amplifier to the memory cell in relation to the value of the programmed data. Wherein a program verification operation is indicated, current is provided from the sense amplifier to the memory cell. Where a program verification operation is not indicated, current is cut off from the sense amplifier.

Abstract: A memory device has multiple bi-directional data paths. One of the multiple bi-directional data paths is configured to transfer data at one speed. Another one of the multiple bi-directional data paths is configured to transfer data at another speed. The memory device has different modes. Depending on a certain mode, the memory device uses different combinations of the multiple bi-directional data paths to transfer data either at a single speed or at multiple speeds. In some cases, the data represents data information to be stored in memory cells of the memory device. In other cases, the data represents control information and feedback information to be transferred to and from internal circuits, besides the memory cells, of the memory device.

Abstract: A semiconductor device is disclosed which increases the data transfer rate in transferring data output from an input/output sense amplifier via a global data bus line by reducing the swing width of the data placed on the global data bus line.

Abstract: A non-volatile semiconductor memory device includes a memory cell array having a plurality of electrically-programmable non-volatile memory cells; a byte scan section detecting errors of said non-volatile memory cells per byte and outputting a status of pseudo-pass even though a number of byte errors are equal to or less than a predetermined allowable number of bytes; and a bit scan section detecting bit errors of said non-volatile memory cells per bit at the time of said status of said pseudo-pass being outputted by said byte scan part, and outputting a status of pseudo-pass even though said number of said bit errors are equal to or less than a predetermined allowable number of bits.

Abstract: A semiconductor device may include a fin structure having source/drain regions and channel fins connected between source/drain patterns. A gate insulation layer may be provided on the channel fins. A gate electrode may include lower gate patterns and an upper gate pattern. The lower gate patterns may extend in a vertical direction and contact the gate insulation layer. The upper gate pattern may extend in a second horizontal direction substantially perpendicular to the first horizontal direction. The upper gate pattern may be connected to upper portions of the lower gate patterns.

Abstract: An integrated circuit memory device, system and method embodiments decode interleaved row and column request packets transferred on an interconnect at a first clock frequency. Separate row decode logic and column decode logic, clocked at a relatively slower second clock frequency, output independent column and row control internal signals to a memory core in response to memory commands in the request packets. An integrated circuit memory device includes an interface having separate row and column decode logic circuits for providing independent sets of row and control signals. A row decode logic circuit includes a first row decode logic circuit that provides a first row control signal, such as a row address, and a second row decode logic circuit that provides a second row control signal. A column decode logic circuit includes a first column decode logic circuit that provides a first column control signal, such as a column address and a second column logic circuit that provides a second column control signal.

Abstract: A memory capable of suppressing disturbance causing disappearance of data in a nonselected memory cell is provided. This memory comprises a memory cell array including a bit line, a word line arranged to intersect with the bit line and memory cells connected between the bit line and the word line, for accessing a selected memory cell thereby deteriorating a remanent polarization in an arbitrary memory cell and thereafter performing recovery for recovering all memory cells to remanent polarizations immediately after a write operation or remanent polarizations subjected to single application of a voltage applied to a nonselected memory cell in the access.

Abstract: A phase locked loop circuit and method of locking a phase. The phased locked loop circuit may include a phase detector receiving an external clock signal and a feedback clock signal and outputting an up signal when a phase of the external clock signal leads a phase of the feedback clock signal and outputting a down signal when the phase of the external clock signal lags the phase of the feedback clock signal, a loop filter circuit increasing a control voltage in response to the up signal and decreasing the control voltage in response to the down signal, and a voltage controlled oscillator circuit receiving the control voltage and directly generating at least n (where n is an integer ?4) internal clock signals. The phased locked loop circuit may also include a voltage controlled oscillator circuit, including at least four loops, receiving the control voltage and generating multiple internal clock signals.

Abstract: An apparatus, a method, and a system for fuse cells are disclosed herein. In various embodiments, a fuse cell may include circuitry to adjust a sensing margin. A fuse cell may include first and second fuse cells, and first and second resistance devices. The first resistance device may be configured to adjust a first voltage output from the first fuse cell, and the second resistance device may be configured to adjust a second voltage output from the second fuse cell. The first and second resistance devices may be configured adjust the first and second voltages asymmetrically.

Abstract: Provided is a phase change memory device including: a phase change memory unit comprising a phase change layer pattern; a laser beam focusing unit locally focusing a laser beam on the phase change layer pattern of the phase change memory unit; and a semiconductor laser unit generating and emitting the laser beam towards the laser beam focusing unit. Thus set or reset operations in the phase change memory device uses laser beams locally applied, thereby reducing the consumption power and preventing destruction or change in information stored in neighboring cell during the operations of unit cell.

Abstract: A memory device includes a number of terminals for transferring input data and output data to and from a memory array. The memory device includes an auxiliary circuit for receiving input auxiliary information associated with the input data and for generating output auxiliary information associated with the output data. The input and output auxiliary information include inverting codes, parity codes, temperature information or time delay information. The input and output auxiliary information are transferred to and from the memory device on the same terminals that the input data and the output data are transferred.

Abstract: A method by which silicon nanostructures may be selectively coated with molecules or biomolecules using an electrochemical process. This chemical process may be employed as a method for coating many different nanostructures within a circuit, each with a different molecular or biomolecular material. The density of devices within a circuit of devices that can be coated with different molecules is limited only by the ability to electronically address each device separately. This invention has applications toward the fabrication of molecular electronic circuitry and toward the fabrication of nanoelectronic molecular sensor arrays.

Abstract: Methods and apparatus that may help reduce standby current in memory devices are provided. By separating equalizing and precharging functions into separate circuit structures, current paths between a source of precharge voltage and a defective wordline (e.g., having an inadvertent short to a bitline due to a manufacturing defect) may be eliminated.

Abstract: A CAM cell is provided that includes: an SRAM cell adapted to store a bit; a data line adapted to provide a corresponding comparand bit; an XOR gate adapted to XOR the stored bit and the comparand bit to provide an XOR output, and a switch adapted to close in response to the XOR output.