Patents Examined by Rijue Mai
  • Patent number: 6877045
    Abstract: Systems, methods, and computer products that improve the performance of computer-implemented I/O operations issued by complex applications that are directed to high-performance disk drives, and that may operate in conjunction with the product marketed under the trademark IBM S/390®. Such high-performance disk drives may include the IBM Shark® that supports the parallel access volumes feature.
    Type: Grant
    Filed: December 18, 2001
    Date of Patent: April 5, 2005
    Assignee: International Business Machines Corporation
    Inventors: David Harold Goode, William Earl Malloy
  • Patent number: 6807584
    Abstract: An apparatus and method for exchanging information between printed circuit board assemblies of the present invention are disclosed. According to the invention, the number of address pins are assigned according to the amount of information to be exchanged between the boards. In a preferred embodiment, where data is transferred in 8 bit words, the amount of data that can be transferred using an address bits is given by 8×2n. Thus, more status information can be exchanged with fewer edge pins. The duplication function between boards can so be more effectively implemented.
    Type: Grant
    Filed: December 26, 2001
    Date of Patent: October 19, 2004
    Assignee: LG Electronics Inc.
    Inventor: Jae-Young Park
  • Patent number: 6792485
    Abstract: The invention provides a data output control apparatus which is suitable for allowing detailed information on a network to be readily obtained. A data output control terminal selects one of printing apparatuses corresponding to a data-format-conversion terminal which allows conversion of data associated with a data print request; outputs the data associated with the data print request to the data-format-conversion terminal allowing conversion of the data and corresponding to the printing apparatus; by the data-format-conversion terminal, converts the data associated with the data print request into data which can be printed by the printing apparatus; and outputs the converted data to the printing apparatus. One or more of data-format-conversion terminals is selected in accordance with the transmission load of the Internet, and data-format-conversion processes are executed by the data-format-conversion terminal.
    Type: Grant
    Filed: June 28, 2001
    Date of Patent: September 14, 2004
    Assignee: Seiko Epson Corporation
    Inventors: Mikio Aoki, Shinya Taniguchi
  • Patent number: 6782436
    Abstract: A method and apparatus for a communication system for facilitating communication on the network. Identification of a network device, preferably a controller or IO device, is based on a physical location of device. Accordingly, the physical location of the network device is determined by a device locator. The physical location of each network device is used to associate a network identifier, i.e., network address, with the network device to facilitate network communication with other devices. The network identifier is associated with the network device in response to a signal transmitted from the network device requesting the network identifier. A mapping method is used to convert a map of physical locations to one or more address tables so as to allow a controlling station to associate the network identifier with the network device for routing messages to and from the device based on the physical location.
    Type: Grant
    Filed: August 16, 2000
    Date of Patent: August 24, 2004
    Inventor: Richard A. Baker
  • Patent number: 6779045
    Abstract: The present invention is in the field of flash memory. More particularly, embodiments of the present invention can enhance an interface of a flash memory device by increasing the number of operations performed per transmission from a media management system. Further, some embodiments of the invention are designed to interface the flash memory device and media management controller via an interconnection attachment and/or driver common to a second type of data storage device, such as a hard drive.
    Type: Grant
    Filed: March 21, 2001
    Date of Patent: August 17, 2004
    Assignee: Intel Corporation
    Inventors: Terry L. Kendall, Richard P. Garner, James W. Bridgewater, Deborah L. See
  • Patent number: 6779052
    Abstract: An electronic apparatus, system and method are provided for controlling different types of electronic devices coupled through a serial bus. The electronic apparatus may include an Integrated Drive Electronics (IDE) port for coupling a plurality of different types of IDE devices, each having information for controlling the device, a memory, and an IEEE 1394 interface for coupling the device to another electronic apparatus, such as a personal computer (PC), through an IEEE 1394 cable. Different types of IDE devices, such as a hard-disk drive or a CD-ROM drive, may be coupled to the IDE port. The PC may read information from each IDE device, convert the information into a format defined by the IEEE 1394 standard, and store the information in a provided configuration read-only-memory (ROM).
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: August 17, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Ken Hatano
  • Patent number: 6779048
    Abstract: A programmable controller (PLC) facilitates modifications to programs running therein, readily accommodates addition and removal of intelligent modules contained therein, and offers good maintenanceability. In the PLC a processing unit of an intelligent module is configured equivalent to a processing unit of a CPU module. Registers and memories of respective intelligent modules are allocated in a memory map of the CPU module to build a hardware configuration which allows the processing unit of the CPU module to read and write the registers and memories of the respective intelligent modules allowing the intelligent modules to be controlled similar to the CPU module. Software running on the CPU module is provided with instructions which indicate that it is executed in an intelligent module but can be processed either by the CPU module or the intelligent module.
    Type: Grant
    Filed: June 22, 2001
    Date of Patent: August 17, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Kenji Seki, Atsushi Ito
  • Patent number: 6779054
    Abstract: In one embodiment, an apparatus is described. The apparatus includes an input/output (I/O) device that is capable of being coupled to a computing system. The device is configured such that, in operation, the I/O device has the capability to interrupt an associated computing system processor based at least in part on a comparison of a threshold value with the quantity of transmit resources available to the I/O device.
    Type: Grant
    Filed: October 5, 2001
    Date of Patent: August 17, 2004
    Assignee: Intel Corporation
    Inventors: William B. Campbell, Linden Minnick
  • Patent number: 6775725
    Abstract: To execute a program in a second chip card, inserted in a terminal in addition to a first chip card, containing data relating to the owner of the first card, the second card communicates with the terminal through exchanges of commands and responses between the two cards, relayed through exchanges of commands and responses, between first card and the terminal. For example, the terminal is a mobile radio telephone terminal with a SIM card as a first card, not requiring any SIM Toolkit protocol interface between the terminal and the second card. Compatibility and adaptation of the second card to the terminal is provided in the preparation for the execution of the program.
    Type: Grant
    Filed: June 5, 2000
    Date of Patent: August 10, 2004
    Assignee: Gemplus
    Inventors: Bruno Basquin, Marc Niccolini
  • Patent number: 6775717
    Abstract: A method and apparatus for reducing latency due to set up time between DMA transfers are described. The method comprises initiating arbitration of DMA channel requests prior to completion of a current DMA transfer; and initiating set up for a next DMA transfer prior to completion of the current DMA transfer according to the arbitration. One implementation of the apparatus includes one or more DMA channel interfaces providing a series of DMA channel requests such that a DMA channel request for a next DMA transfer is provided before a current DMA transfer is completed; and a DMA controller that initiates arbitration of DMA channel requests after they are provided by the one or more DMA channel interfaces and before the current DMA transfer is completed, and initiates set up for the next DMA transfer prior to completion of the current DMA transfer according to the arbitration.
    Type: Grant
    Filed: June 21, 2002
    Date of Patent: August 10, 2004
    Assignee: Integrated Device Technology, Inc.
    Inventors: Ming Tang, Jiann Liao
  • Patent number: 6775718
    Abstract: A direct memory access control system supplies the respective status signals indicating timings of the read data effective state or writable state between the input/output interface and memory interface, both interfaces maintain the read data effective state and writable state of the input/output memory and synchronous memory under control until the later timing comes up. Consequently, it is possible to match the read data effective timing and writable timing of the synchronous memory and input/output memory, thus making possible flyby transfer of data between both memories.
    Type: Grant
    Filed: August 22, 2001
    Date of Patent: August 10, 2004
    Assignee: Fujitsu Limited
    Inventors: Toshiaki Saruwatari, Atsushi Fujita
  • Patent number: 6775716
    Abstract: A high-performance DMA controller for controlling data transfer between a main storage means holding various kinds of data and a plurality of local storage means, comprises: an interface for generating a control signal for the main storage means; a data I/O unit for controlling I/O of data; a parameter holding unit for holding various kinds of parameters that are required for execution of data transfer; a data transfer request receiver for receiving requests of data transfer; and a start command receiver for receiving a start/stop command of the data transfer controller. The data transfer request receiver receives, from a data transfer request source, reservations of plural data transfer requests comprising execution priority information and local storage means type information, each information being arbitrarily set by the data transfer request source, and holds the local storage means type information in association with each execution priority information.
    Type: Grant
    Filed: May 18, 2001
    Date of Patent: August 10, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masayoshi Tojima, Yasuo Kohashi, Tomonori Yonezawa
  • Patent number: 6772247
    Abstract: A circuit that merges and aligns data that resides in a buffer entry is described. The data residing in the buffer entry is divided into a prepend portion and a payload portion. The prepend and the payload portions of the data are each defined, in part, by a length and an offset. Given the lengths and offsets, the circuit fetches the data from the buffer entry, merges the data, and aligns the data.
    Type: Grant
    Filed: November 19, 2002
    Date of Patent: August 3, 2004
    Assignee: Intel Corporation
    Inventor: Raymond Ng
  • Patent number: 6772233
    Abstract: A portable card type data storage device with a large capacity and low power consumption is provided which enalbes two storage mediums with different features to be installed into a single slot of an information processing device. The card type data storage device 100 of the invention includes a case 10 having a connection slot 10a, a first connector 11 adapted to be inserted into and connected with a connection slot 201 of an information processing device such as a PC 200, a hard disk 13 housed in the case 10, a second connector 12 for connection with a semiconductor memory 18 inserted into the connection slot 10a, and a storage device control section 20.
    Type: Grant
    Filed: August 28, 2001
    Date of Patent: August 3, 2004
    Assignee: Fujitsu Limited
    Inventors: Atsuo Iida, Keiju Okabayashi, Shinji Kanda, Mitsunori Fukazawa
  • Patent number: 6766386
    Abstract: A novel method and interface is provided for conducting read data transfers between an initiator device on a single-transaction bus and a target device on a split-transaction bus. Embodiments of the present invention permit the initiator device to “post” a read request for a specified amount of data from a specified address on the split-transaction bus to an interface that resides between the single-transaction bus and the split-transaction bus. The requested read data is then retrieved over the split-transaction bus and presented in a high-speed memory within the interface for direct access by the initiator device over the single-transaction bus. Latency is avoided because the initiator device is not required to wait for the emergence of the requested read data from the split-transaction bus but, instead, may continue to perform other activities on the single-transaction bus and then obtain the requested read data at a later time.
    Type: Grant
    Filed: August 28, 2001
    Date of Patent: July 20, 2004
    Assignee: Broadcom Corporation
    Inventors: William Gordon Keith Dobson, Joel Danzig
  • Patent number: 6766390
    Abstract: The present invention is to provide a system connection adapter and a terminal device, which allow a function which is newly developed and added by a maker on a system A to be handled on an open system B even in the case where the system A which is an existing system for supervising and controlling such as an air conditioning apparatus and a lighting apparatus installed in a building or at home is connected with the open system B which is made up by using a protocol different from that used by the system A. This allows for ease in expanding functions. According to the system connection adapter, a conventional command, which is the original of the system A, and therefore not specified in the open system B and has no correspondence available, is added with a frame header B by a frame encapsulation and decapsulation means, and transmitted in its original form.
    Type: Grant
    Filed: November 27, 2002
    Date of Patent: July 20, 2004
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Noriyuki Komiya, Noriyuki Kushiro
  • Patent number: 6763406
    Abstract: A method of communicating a data word via a bus includes driving the data word onto the bus in whichever one of a true polarity form and a complement polarity form that requires fewer bus lines to change state relative to a present state of each bus line, and providing an indicator signal to the bus to indicate which polarity form of the data word is driven onto the bus. The data word and the indicator signal may be received from the bus, and the polarity form of the data word is conditionally inverted in response to the indicator signal. A noise reduction system includes, for one embodiment, a sending circuit which compares each bit of a data word to be next communicated onto the bus against a corresponding bit of the present data word on the bus. If more than half the bits differ, then the next data word is inverted to form a complement next data word.
    Type: Grant
    Filed: February 1, 2001
    Date of Patent: July 13, 2004
    Assignee: Integrated Device Technology, Inc.
    Inventors: William L. Devanney, Robert J. Proebsting
  • Patent number: 6763398
    Abstract: A storage controller for redundant arrays of independent disks (RAID) comprises a daughter card containing a standardized controller core, which is mated to one of a number of customizable controller interface cards. The controller core card includes high performance elements such as a processor, cache memory, CRC circuitry, a host port, and a storage port. All operational communication with non-core components occurs via the host port and the storage port through the controller interface card. The controller core card monitors and configures communications between the host and the storage array. Each controller interface card is populated with components and connectors particular to the respective application or RAID system. The size and layout of the controller interface card may also be customized to the particular application. Sharing the same controller core card among various RAID controllers lowers the cost and time-to-market for customized RAID systems.
    Type: Grant
    Filed: August 29, 2001
    Date of Patent: July 13, 2004
    Assignee: International Business Machines Corporation
    Inventors: William A. Brant, Randall F. Horning
  • Patent number: 6763469
    Abstract: Security systems for computers connected to networks transmitting packets are disclosed. One disclosed system includes a security agent and a local security device featuring a network hardware connector, a computer hardware connector, a flash memory and a microprocessor to perform a software instruction. The security agent closes the security device by altering a setting of a bit of the flash memory. Further disclosed is a firewall on a single chip for providing security to a network transmitting packets. The firewall includes a network hardware connector, a memory for storing a rule and a software instruction for examining each packet and a microprocessor. Preferably the rule is configurable by a user and the memory includes at least one displayable Web and Web server functionally for serving a Web page and accepting a command from a user such that said at least one rule is determined by the command.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: July 13, 2004
    Assignee: Telecom Italia S.p.A.
    Inventor: Gad Daniely
  • Patent number: 6763408
    Abstract: An interface switching device is connected to a keyboard unit and a computer. Two data lines, a power-supply line, and a ground line, which are provided at the interface switching device, are respectively connected to a data line, a clock line, a power-supply line, and a ground line, which are provided at the keyboard unit. An unused line is connected to an identification line. At the computer, the unused line, and the power-supply line or the ground line, are short-circuited. When the interface switching device is connected, a keyboard is notified of a voltage as identification information which is fixed at a power-supply voltage or zero volts.
    Type: Grant
    Filed: August 16, 2000
    Date of Patent: July 13, 2004
    Assignee: Alps Electric Co., Ltd.
    Inventor: Yuko Sonoda