Abstract: A data queue system comprises plural memory blocks defined in memory, and a queue which comprises a number of memory blocks each including a link to the following block in the data queue. A queue descriptor includes identities which identify: the final block in the queue, the memory location where the most recent read commit occurred (and optionally an offset from a predetermined location in that block), the memory location where the most recent write commit occurred (and optionally an offset from a predetermined location in that memory block), the size of the blocks, the memory location the most recent write occurred, the number of unused blocks, the number of blocks which contain data to be read, the type of data queue, the memory location where the most recent read occurred and the number of blocks which have been read since the most recent read commit.

Abstract: The density for any generation of Standard In-Line Memory Module (SIMM), or Dual In-Line-Memory Module (DIMM), chipset used to provide computer Random Access Memory (RAM), can be multiplied by surface-mounting multiple banks of SIMMs or DIMMs, where each bank occupies one side of a printed-circuit board (PCB) and at least a second PCB is connected to a first PCB, which is in turn connected through the standard edge connectors to the bus, with the banks connected through shared and controlled input-and-output lines, and wherein a single standard controller directs address-oriented storage to the corresponding portion of the stacked and connected banks.

Abstract: A peripheral interface circuit for handling graphics responses in an I/O node of a computer system. A peripheral interface circuit includes a buffer circuit coupled to receive packet commands. The buffer circuit includes a plurality of buffers each corresponding to a respective virtual channel of a plurality of virtual channels for storing selected packet commands that belong to the respective virtual channel. The peripheral interface circuit may determine whether a given one of the received packet commands is a graphics response belonging to a particular respective virtual channel. In response to determining that the given packet command is a graphics response belonging to the particular respective virtual channel, the buffer circuit may cause the given packet command to bypass the plurality of buffers.

Abstract: A data-output-control apparatus is provided which can easily acquire detailed information on a network and which, for outputting the detailed information, does not require a portable terminal to increase memory and is suitable to reduce a processing load on the portable terminal. A data-output-control terminal links by the Internet so as to communicate with a portable terminal carried by a user, printers located in areas, and WWW servers, and performs, when receiving a data-printing request from the portable terminal, acquiring data according to the data-printing request from the WWW server, selecting any one of a plurality of printers, and outputting the acquired data to the selected printer.

Abstract: When a user process issues an input/output request in a process performed in response to the input/output request generated by the user process, the input/output request is queued in the input/output request list which is a queue in a list format on the user space side. On the kernel side, when a input/output request in the input/output request list is processed, the status is changed into ‘processed’, and a list element whose status indicates ‘processed’ is removed from the request list on the user space side. On the kernel side, a thread for performing a process in response to an input/output request is divided into a plurality of threads, and the CPU is released to another thread before completion of the process.

Abstract: A processing system includes a processing device and a host processor operatively coupled to the processing device via a system bus, and implements a scatter gather data transfer technique. The host processor is configurable to control the transfer of information to or from scattered or non-contiguous memory locations in a memory associated with the processing device, utilizing a data structure comprising a single descriptor. An information transfer bandwidth of the system bus is thereby more efficiently utilized than if a separate descriptor were used for transfer of information involving each of the non-contiguous memory locations.

Abstract: Described is a system and method by which data accesses to information related to a CMOS device are synchronized. A special “operation region” is provided through which the information is accessed. More specifically, a “CMOS Operation Region” is enabled through which CMOS information is read or written. When an AML interpreter performs a read or write instruction to the CMOS operation region, the ACPI system passes that instruction to a process for handling that operation region, in this example the system kernel. The process may include mechanisms that synchronize accesses to the Operation Region so that a load or store operation is fully completed prior to allowing a subsequent load or store operation. In this way, the information associated with the CMOS that is loaded in memory is not corrupted by asynchronous accesses.

Abstract: A remote control device provides commands and options based on the configuration of components in a user's environment, and based on a defined user activity. A storage device contains a user profile that includes the configuration of components at the user's environment, and defined set of user activities, such as “watching television”, “viewing a movie”, “watching a sports program”, and so on. Each user activity has a corresponding mapping of keys on the remote control device to facilitate the user activity. When the user identifies a preferred activity, the remote control device communicates commands to the components of the system to support the activity, and subsequently communicates commands to each component corresponding to this activity. A user may define multiple user activities, and the storage device may contain configurations and activities from multiple users.

Abstract: A device is presented including a host controller. A host controller driver is connected to the host controller. The host controller arranges queue element transfer descriptors (qTDs) in a circularly linked order. Also presented is a method including determining whether execution of a first queue element transfer descriptor (qTD) in a first bank including many qTDs results in a short packet condition. Following an alternate pointer in the first bank that points to a second bank if execution of the first qTD resulted in the short packet condition. Following a next pointer to a second qTD in the first bank if the execution of the first qTD completed normally. Also executing the second qTD in the first bank. The qTDs in the first bank and the second bank are circularly linked.

Abstract: A plurality of independent cache units and nonvolatile memory units are provided in a disk controller located between a host (central processing unit) and a magnetic disk drive. A plurality of channel units for controlling the data transfer to and from the central processing unit and a plurality of control units for controlling the data transfer to and from the magnetic disk drive are independently connected to the cache units and the nonvolatile memory units through data buses and access lines.

Abstract: A disk cache translation system for mapping data record lengths between systems having different data record lengths. Command queue (315) maps into initiation queue (305) to allow I/O manager (230) to manage I/O requests from operating system (125). I/O requests are statused by I/O manager (230) using status queue (325). Store-thru cache (280) provides a single interface to disk array (270) such that disk array write operations are reported complete only when user memory (250), I/O cache (280) and disk array (270) are synchronized. Data record length translations are performed using I/O cache (280) in order to align data record length differences between operating system (125) and I/O device (270).

Abstract: A method for data streaming by a SCSI system using a Packetized SCSI Protocol includes transferring a data packet information unit in a Packetized SCSI Protocol Data In phase between a SCSI target and a SCSI initiator over a SCSI bus. In this method, the SCSI target generates a signal on the SCSI bus in the Packetized SCSI Protocol Data In phase to indicate whether a header packet information unit or another data packet information unit is to be transmitted next in the Packetized SCSI Protocol Data In phase to the SCSI initiator.

Abstract: A two-dimensional hardware control block execution queue includes a plurality of initiator queues where each initiator queue includes at least one hardware control block. Each of the initiator queues is a queue of hardware command blocks, e.g., SCSI control blocks (SCBs) for a specific initiator device on the I/O bus. There is only one initiator queue for each initiator device. One head hardware control block, and only one head hardware control block of each initiator queue, is included in a common queue. Only a common queue head pointer is stored in a memory. An initiator command block tail pointer is stored in the head hardware control block for that initiator queue.

Abstract: The inventive method allows to secure data relating to users of a public key infrastructure who may present certificates (11) at an institution (30) in order to initiate transactions. For this purposes the institution (30) uses and securely stores a secret key or a key pair which is designed for encrypting and decrypting data. Based on an agreement between a certificate holder and the institution (30), corresponding relational data are generated. Then said relational data are encrypted with the institution's (30) secret key or the first key of said key pair. Subsequently the encrypted relational data are integrated into the certificate (11) which preferably adheres to ITU recommendation X.509 version 3.

Abstract: A method, system, and computer program product for logging events in a data processing system is provided. In one embodiment, responsive to a determination that a situation exists preventing a primary logger from executing a logging task, a swappable adaptive logger is created, which in turn is pointed to a boot logger created by a swappable adaptive log engine. Event information is then logged to the boot logger. For example, the boot logger may write event information to memory or to a file if the logging database is unavailable. When the primary logger becomes configured and functional, the swappable adaptive logger swaps the boot logger for the primary logger and begins writing event information to the primary logger.

Abstract: A data processing arrangement comprises a plurality of processors and a memory interface via which the processors can access a collective memory. The memory interface comprises an interface memory (SRAM) for temporarily storing data belonging to different processors. The memory interface also comprises a control circuit for controlling the interface memory in such a manner that it forms a FIFO memory for each of the different processors. This makes to possible to realize implementations at a comparatively low cost in comparison with a memory interface comprising a separate FIFO memory for each processor.

Abstract: A universal expansion module interfaces a logic controller to a plurality of types of input/output expansion modules that communicate input/output data between the controller and automated devices. A communication interface establishes communication between the controller and at least one of the plurality of types of an input/output expansion module. An expansion module having a physical configuration accommodates signals from the plurality of types of input/output expansion modules.

Abstract: A method and system for decreasing the time needed for a mirror split operation in a data storage device by preparing for the mirror split operation during a time interval between notification of an intended mirror split operation and the subsequent time of the mirror split operation. In general, local writes are processed preferentially and asynchronously with respect to corresponding mirror writes, but, after receiving a split advance warning, the data storage device controller preferentially processes backlogged mirror writes in order that the mirrored data storage units are nearly consistent at the time that the intended mirror split operation request is received.

Abstract: An integrated display personal computer in which a display unit such as a liquid-crystal panel and a PC unit are integrated into a single housing. The display unit can be used as a display for other notebook-sized personal computer or as that for a potable DVD player. The integrated display personal computer is provided with an input terminal and a signal selector for supplying either of a signal from the PC unit and a signal from the other device to the display unit selectively. Provided is a power distributor for supplying the electric power to the PC unit and the display unit selectively in response to the operation of the signal selector. When the signal from the PC unit is supplied to the display device, the power source power distributor supplies the electric power to both the PC unit and the display unit, while when the signal from the other device is supplied to the display device, the power distributor supplies the power to the display unit.

Abstract: A control system allows a user to access an input/output device over a communication network using a web browser. The system includes an Internet web site between the network and the input/output module. The web site runs from an Ethernet board coupled directly to the input/output module back plane and includes a HTTP protocol interpreter, an input/output module, a TCP/IP stack, and an Ethernet board kernel. The web site provides access to the input/output module by a user at a remote location through the Internet. The web site translates the industry standard Ethernet, TCP/IP and HTTP protocols used on the Internet into data recognizable to the input/output module. Using this interface, the user can input or retrieve all pertinent data regarding the operation of the input/output device.