Abstract: Systems and methods of processing network packets are described. These systems and methods provide improved packet processing results by logically and physically separating packet header processing functions from packet data processing functions. In this way, a network processing system may perform network handling operations and data processing operations substantially in parallel. One or more embodiments feature a network adapter for exchanging with a computer network information in the form of packets each including a packet header and packet data. The network adapter includes a packet parser configured to parse an information packet into a packet header and packet data and to direct the packet header to a first memory address for protocol processing and to direct packet data to a second memory address for data processing.

Abstract: The invention provides the ability to interactively select and configure a product among a set of related products based on availability and compatibility of features and options. It does not impose an order in the selection of products, features or options; only valid selections can be made at any time. To create an electronic representation of the product information to achieve the above goal, the invention provides a framework for defining a systems by defining the components of the system using elements contained in a parts catalog and defining relationships between the components of a system. A configuration system validates a configuration using the system definition, the current state of the configuration and user input.

Abstract: A computer network system includes a plurality of computers each including a central processing unit (CPU), a memory and at least one peripheral device, a connection fabric having selectable first and second sides, the first side being coupled to a first computer of the plurality of computers and the second side being coupled to at least a second computer of the plurality of computers. Each of the first and second computers performs a negotiation to determine which one of the first and second computers controls resources of the other of the first and second computers.

Abstract: A mechanism that allows an application program running on a processor, to send data to a device using a medium that temporarily stores data and changes the order of the data dispatch on the way to the device. An inventive Random-In-First-Out (RIFO) buffer or memory device that restores the original order is provided. Several alternative approaches for implementing the RIFO control mechanisms for write efficiency and correctness. Method for use in conjunction with a data processing system having a host processor executing write instructions and communicating results in the form of symbols generated by the write instructions to at least one hardware device coupled to the host processor for receiving the symbols from the host processor, where the method preserves a predetermined order in which the symbols are received by the hardware device.

Abstract: Techniques for converting input data from a multiplicity of sources that are mutually asynchronous, to a single, common synchronous format for local processing by an information processor. Logical operations are described which control first-in-first-out (“FIFO”) buffers to align all inputs to a predetermined point in the data flow or processing sequence, and which maintain clock-by-clock alignment of the input data sequences for an indefinite period of time thereafter.

Abstract: A LAN interface is provided that can reduce the power consumption of the whole of a terminal in an unnecessary state of a LAN interface. The LAN interface includes a link pulse detector 16 that operates on a predetermined voltage supplied via the I/O bus 11 and detects a link pulse transmitted from a counter device connected to the connection port 15. When detecting a link pulse sent from a counter device, the link pulse detector 16 controls the LAN controller 13 and the isolation section 12 to controllably bring them to an operation state thereof. When not detecting a link pulse sent from the counter device, the link controller 13 controls the LAN controller 13 and the isolation section 12 to bring them to a non-operation state.

Abstract: The present invention is directed to a system and method of retaining peripheral ordering. A method for retaining peripheral ordering in an information handling system may include reading an ordered peripheral list (OPL) from a nonvolatile memory. A list of active peripherals attached to an I/O interface controller is obtained. An order of peripherals from the ordered peripheral list (OPL) is identified and assignments are assigned to the active peripherals attached to the I/O interface controller corresponding to the ordered peripheral list (OPL).

Abstract: A method, system, and apparatus for modifying bridges within a data processing system to provide improved performance is provided. In one embodiment, the data processing system determines the number of input/output adapters connected underneath each PCI host bridge. The data processing system also determines the type of each input/output adapter. The size and number of buffers within the PCI host bridge is then modified based on the number of adapters beneath it as well as the type of adapters beneath it to improve data throughput performance as well as prevent thrashing of data. The PCI host bridge is also modified to give load and store operations priority over DMA operations. Each PCI-to-PCI bridge is modified based on the type of adapter connected to it such that the PCI-to-PCI bridge prefetches only an amount of data consistent with the type of adapter such that excess data is not thrashed, thus requiring extensive repetitive use of the system buses to retrieve the same data more than once.

Abstract: A device, method and computer program for communicating between a device controller and an industry standard bus. This device method and computer program requires no modification of the core logic of the device driver even though the data and commands transmitted between the device controller and the bus require a different format and different length commands. This device utilizes a convert and store logic unit to convert commands from the core unit to a reduced bit format suitable for the industry standard bus.

Abstract: An improved modem architecture and associated method are disclosed that integrate modem functionality and line-side isolation functionality while also providing a modem interface that allows command and data mode control.

Abstract: A novel and sophisticated direct memory access (DMA) controller that can operate in either “fly-by” mode, “dual-cycle” mode, or “flow-through” mode. The DMA controller of the present embodiment supports a parametrizable number of channels, each of the channels providing support for one of the prior-noted modes of operation. The DMA controller of the present embodiment serves as bus master on the host bus and has the ability to interface with all the devices on the system. The DMA controller of the present embodiment is also optimized for zero wait state sequential transfers on the host bus. Further, the DMA controller of the present embodiment also houses an internal arbiter with programmable priority to choose arbitrate between the different channels, should more than one master that interface to the DMA controller request access to the host bus.

Abstract: A communication interface system including a computer and a handheld device that communicate with each other via respective communication ports. The computer communication port is a serial port or an infrared transceivers conveniently located on the front bezel of the computer. In serial embodiments, the computer executes the appropriate driver and interface applications to enable transfer of information to the handheld device. In infrared embodiments, the computer includes a microcontroller, an I2C bus and memory, where the microcontroller implements infrared communication protocol. Alternatively, the computer may further include a management processor that either replaces or cooperates with the microcontroller. Auxiliary power may enable handheld communications when the computer is shut down. The handheld device interfaces with the computer communication port to retrieve and display the status information.

Abstract: A user specifies image data to be transferred and the conversion form of the image data. An information processing device instructs an image data obtaining device to transfer the specified image data. The transferred image data is converted into data in the form specified by the user. The image data to be transferred and the specification of its conversion form are simultaneously received, so that the image data is transferred and converted at the same time. Accordingly, user operations are reduced and user operability can be improved.

Abstract: A method for securing port bypass circuit settings is presented comprising issuing one or more command(s) to one or more inputs of a general purpose input/output (GPIO) system, wherein the command(s) cause a first output of the GPIO system associated with a first input of the multiple inputs to issue a control signal to a latch associated with a port bypass circuit (PBC) addressed in the received command(s), and a second output of the GPIO system associated with a second of the multiple inputs of the GPIO system to issue a clock signal to a latch associated a PBC addressed in the received command(s). If command(s) received at the first and second inputs are consistent with changing the state of a common PBC, the control signal and the clock signal are sent to a single latching device, which latches the control signal to the addressed PBC changing the state of the PBC. If the command(s) are not consistent, the control and clock signal(s) are not received by a common latch, and the PBC states remain unchanged.

Abstract: A data processing arrangement comprises a plurality of processors. These processors share a collective memory. The arrangement comprises private buses. A private bus enables data communication exclusively between a processor and the collective memory. A memory interface provides access to the collective memory in data bursts while it produces substantially steady data streams on the private buses.

Abstract: A data storage system wherein a host computer is coupled to a bank of disk drives through an interface. The interface has a plurality of directors and a memory interconnected by a buss. The directors control data transfer between the host computer and the bank of disk drives as such data passes through the memory. The interface includes a plurality of ESCON adapters, a front end portion of the directors being coupled between the host computer and the busses through the ESCON adapters. Each one of such adapters includes a plurality of adapter ports each one being coupled to a corresponding port of the host computer. Each one of the adapters also includes a plurality of adapter board gate arrays and a plurality of optic interfaces. Each one of the optic interfaces is coupled between a corresponding one of the adapter port and a corresponding one of the adapter board gate arrays. Each coupled optic interfaces and gate array provides a corresponding one of a plurality of channels for the data.

Abstract: A process is described for implementing a plurality of function modules stored in an image forming apparatus. The process installs a hardware module without need to install a software module. An input of a predetermined key code corresponding to the specific function completes the installation of the specific function when the image forming apparatus additionally requires the specific function.

Abstract: A vehicle-mounted electronic control apparatus comprises: a main CPU including a first nonvolatile memory in which at least control programs and control constants, in correspondence with types of controlled vehicles, transmitted from an external tool are written, the main CPU including a first RAM for calculation processing; a sub CPU including a second nonvolatile memory in which programs for input/output processing are written and a second RAM for calculation processing; and a serial-parallel converter for serial communication adapted to transmit a plurality of input signals, which are input to the sub CPU, to the main CPU, wherein a plurality of filter constants corresponding to the plurality of input signals are stored in at least one of the first and second nonvolatile memory; and the sub CPU has a digital filter section adapted to perform predetermined calculation based on the filter constants to transmit a result of the calculation to the main CPU.

Abstract: A programmable logic controller (PLC) having a process means, a sampling means, and a diagnostic means, to invoke discrete incremental states representing an infinite number non discrete intermediate input values from electromechanical sensors such as rheostats, resistive pressure gauges, resistive thermal sensors, or the like, within logic based program control sequences. A methodology to employ an infinite number of non discrete intermediate values of voltage, current, or resistance, represented by user-defined incremental states for invoking logic based control sequences to operate electromechanical devices such as solenoids, relays, indicating lamps, or the like. A system comprised of an apparatus and methodology in a singular or plurality of devices provides an operational means to observe, filter, and control, various electrical characteristics for electromechanical devices.

Abstract: A clock module operates in conjunction with the generation of the bus-clock signal to provide a combination of module-clocks that can be relied upon to provide an adequate safety margin for data transfers among processing modules at the speed of the bus-clock. In a preferred embodiment, a system-clock generates the bus-clock and a sample-clock, the sample-clock having a predetermined phase relationship with respect to the bus-clock. Base-clocks at each of the frequencies required for each processing module are generated in the conventional manner, and, in accordance with this invention, are sampled by the sample-clock to produce sampled module-clocks that are provided to each corresponding processing module. By sampling each base-clock with a sample-clock that has a corresponding predetermined phase relationship with respect to the bus-clock, each module-clock will have a predetermined phase relationship with respect to the bus-clock.