Abstract: First, an offset spacer including a stacked film of insulating films is formed on the upper surface of the semiconductor layer, the side surface of the gate electrode, and the side surface of the cap film. Next, a part of the insulating films is removed to expose the upper surface of the semiconductor layer. Next, in a state where the side surface of the gate electrode is covered with the insulating films, an epitaxial layer is formed on the exposed upper surface of the semiconductor layer. Here, among the offset spacers, the insulating film which is a silicon nitride film is formed at a position closest to the gate electrode, and the position of the upper end of the insulating film formed on the side surface of the gate electrode is higher than the position of the upper surface of the gate electrode.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a gate structure on the substrate; forming an epitaxial layer adjacent to the gate structure; forming an interlayer dielectric (ILD) layer on the gate structure; forming a first contact hole in the ILD layer adjacent to the gate structure; and forming a cap layer in the recess, in which a top surface of the cap layer is even with or lower than a top surface of the substrate.

Abstract: A substrate includes on its surface an array of dual stack semiconductor fins, each fin comprising a monocrystalline first portion, a polycrystalline second portion, and a mask third portion. Trenches between the fins are filled with shallow trench isolation (STI) oxide and with polycrystalline material, after which the surface is planarized. Then a second mask is produced on the planarized surface, the second mask defining at least one opening, each defined opening extending across an exposed fin. A thermal oxidation is performed of the polycrystalline material on either side of the exposed fin in each defined opening, thereby producing two oxide strips in each defined opening. Using the second mask and the oxide strips as a mask for self-aligned etching, the material of the exposed dual stack fins is removed and subsequently replaced by an electrically isolating material, thereby creating gate cut structures.

Abstract: A radiation-emitting semiconductor body includes a semiconductor layer sequence including an active region that generates radiation, an n-conducting semiconductor layer and a p-conducting semiconductor layer, wherein the active region is arranged between the n-conducting semiconductor layer and the p-conducting semiconductor layer and the p-conducting semiconductor layer includes a first doping region with a first dopant and a second doping region with a second dopant different from the first dopant, and the p-conducting semiconductor layer includes a further doping region doped with the first dopant and has a thickness of at most 2 nm.

Abstract: A display device may include a display module and a cushion layer. The display module may include a display panel, which includes a circuit layer, a light emitting device layer on the circuit layer, and an encapsulation layer encapsulating the light emitting device layer, and a window substrate, which is on the display panel. A pattern including a vibration attenuating line extending in a direction may be defined by the cushion layer, and the cushion layer may be below the display module. The vibration attenuating line may be spaced apart from an edge of the cushion layer by a first length, and the first length may be a value obtained by dividing a sound speed in the display module by a natural frequency of the display module.

Abstract: Thin-film electronic devices such as LED devices and field effect transistor devices are fabricated using a non-destructive epitaxial lift-off technique that allows indefinite reuse of a growth substrate. The method includes providing an epitaxial protective layer on the growth substrate and a sacrificial release layer between the protective layer and an active device layer. After the device layer is released from the growth substrate, the protective layer is selectively etched to provide a newly exposed surface suitable for epitaxial growth of another device layer. The entire thickness of the growth substrate is preserved, enabling continued reuse. Inorganic thin-film device layers can be transferred to a flexible secondary substrate, enabling formation of curved inorganic optoelectronic devices.

Abstract: A semiconductor device comprises a substrate. A plurality of electrode layers and a plurality of insulating layers are formed in an alternating stack above the substrate. A semiconductor column extends through the plurality of electrode layers and the plurality of insulating layers. The semiconductor column comprises a single-crystal semiconductor material on an outer peripheral surface facing the electrode and insulating layers. First insulating films are formed between the semiconductor column and the electrode layers. The first insulating films are spaced from each other along the column length. Each first insulating film corresponds to one electrode layer. A charge storage layer is between each of the first insulating films and the electrode layers. A second insulating film is between the charge storage layer and each of the electrode layers.

Abstract: A photodetector comprising a contact layer; an absorbing region positioned such that light admitted passes into the absorbing region; a diffractive region comprising at least one diffractive element operating to diffract light into the absorbing region; the configuration of the photodetector being determined by computer simulation to determine an optimal diffractive region and absorbing region configuration for optimal quantum efficiency for at least one predetermined wavelength range, the diffractive region operating to diffract light entering through the contact layer such that phases of diffracted waves from locations within the photodetector including waves reflected by sidewalls and waves reflected by the diffractive elements form a constructive interference pattern inside the absorbing region.

Abstract: A light emitting device and a display apparatus including a phase shifting mirror are provided. The light emitting device includes a first electrode, a light emitting structure, a second electrode, and a phase shifting mirror. The phase shifting mirror has a number of patterns arranged in a periodic manner with an interval between adjacent patterns. Each pattern has a top surface and a side surface between the top surface of the respective pattern and the top surface of the first electrode. A first width at a bottom portion of the respective pattern directly adjacent to the top surface of the first electrode is greater than a second width of the top surface of the respective pattern, and the first width and the second width are less than a wavelength of light generated in the light emitting structure.

Abstract: A semiconductor package includes a frame having a recess on which a stopper layer is disposed, a semiconductor chip including a body having a first surface on which a connection pad is disposed and a second surface opposing the first surface, and a through-via penetrating through at least a portion of a region between the first surface and the second surface, the second surface facing the stopper layer, an encapsulant covering at least a portion of each of the frame and the semiconductor chip and filling at least a portion of the recess, a first connection structure disposed on a lower side of the frame and on the first surface of the semiconductor chip and including a first redistribution layer, and a second connection structure disposed on an upper side of the frame and on the second surface of the semiconductor chip and including a second redistribution layer.

Abstract: The disclosure provides a plasma source and an excitation system for excitation of a plasma, and an optical monitoring system. In one embodiment the plasma source includes: (1) a coaxial resonant cavity body having an inner length, and including a first end, a second end, an inner electrode and an outer electrode, (2) a radio frequency signal interface electrically coupled to the inner and outer electrodes at a fixed position along the inner length and configured to provide a radio frequency signal to the coaxial resonant cavity body, (3) a window positioned at the first end of the coaxial resonant cavity body, and (4) a mounting flange positioned proximate the window at the first end of the coaxial resonant cavity body and defining a plasma cavity, wherein the window forms one side of the plasma cavity and isolates the coaxial resonant cavity body from plasma in the plasma cavity.

Abstract: A semiconductor device includes a semiconductor layer, having an active region, in which a functional element is formed, a first impurity region of a first conductivity type, formed at a surface layer portion of the semiconductor layer, a second impurity region of a second conductivity type, formed at a surface layer portion of the first impurity region and defining the active region, and a well region of the second conductivity type, formed along a periphery of the second impurity region at the surface layer portion of the first impurity region and having an inner side edge portion positioned at the second impurity region side, and an outer side edge portion positioned at an opposite side with respect to the second impurity region and having a second conductivity type impurity concentration lower than a second conductivity type impurity concentration of the inner side edge portion.

Abstract: A radiation-emitting semiconductor body includes a semiconductor layer sequence including an active region that generates radiation, an n-conducting semiconductor layer and a p-conducting semiconductor layer, wherein the active region is arranged between the n-conducting semiconductor layer and the p-conducting semiconductor layer and the p-conducting semiconductor layer includes a first doping region with a first dopant and a second doping region with a second dopant different from the first dopant, and the p-conducting semiconductor layer includes a further doping region doped with the first dopant and has a thickness of at most 2 nm.

Abstract: An interconnect and a method of forming an interconnect for a semiconductor device is provided. Conductive lines having different widths are formed. Wider conductive lines are used where the design includes an overlying via, and narrower lines are used in which an overlying via is not included. An overlying dielectric layer is formed and trenches and vias are formed extending through the overlying dielectric layer to the wider conductive lines. Voids or air gaps may be formed adjacent select conductive lines, such as the narrower lines.

Abstract: An imaging device includes a substrate including a photoelectric conversion portion and an insulating layer formed to cover at least a part of the photoelectric conversion portion. The insulating layer contains silicon, nitrogen, and chlorine. In an embodiment, in at least a part of the insulating layer, a ratio of silicon atoms bonded to one, two, or three nitrogen atoms and not bonded to an oxygen atom is not more than 20% in silicon atoms contained in at least the part.

Abstract: A semiconductor integrated circuit includes: an n?-type support layer; a p-type well region provided in an upper portion of the support layer; a p+-type circuit side buried layer provided inside the well region; an n+-type first and second terminal regions provided in an upper portion of the well region and above the circuit side buried layer; a p-type body region provided in an upper portion of the support layer; a control electrode structure provided in a gate trench; a p+-type output side buried layer provided inside the body region so as to be in contact with the control electrode structure; and an n+-type output terminal region provided in an upper portion of the body region and above the output side buried layer, wherein an output stage element having the output terminal region is controlled by a circuit element including the first and second terminal regions.

Abstract: Transistors may be manufactured with a shared drain to reduce die area consumed by circuitry. In one example, two transistors can be manufactured that include two body regions that abut a shared drain region. The two transistors can be independently operated by coupling terminals to a source and a gate for each transistor and the shared drain. Characteristics of the two transistors can be controlled by adjusting feature sizes, such as overlap between the gate and the shared drain for a transistor. In particular, two transistors with different voltage requirements can be manufactured using a shared drain structure, which can be useful in amplifier circuitry and in particular Class-D amplifiers.

Abstract: According to one embodiment, a semiconductor storage device includes a first charge storage part, a first insulating part, a second charge storage part, a second insulating part, a first select transistor, and a hollow part. The first charge storage part is at a first position separated from a surface of a substrate by a first distance in a third direction. The first select transistor is at a second position separated from the surface of the substrate by a second distance in the third direction. The second distance is greater than the first distance. The hollow part is up to a third position in the third direction separated from the surface of the substrate by a third distance in the third direction. The third distance is greater than or equal to the first distance and shorter than or equal to the second distance.

Abstract: With an increase in the definition of a display device, the number of pixels is increased, and thus the numbers of gate lines and signal lines are increased. Due to the increase in the numbers of gate lines and signal lines, it is difficult to mount an IC chip having a driver circuit for driving the gate and signal lines by bonding or the like, which causes an increase in manufacturing costs. A pixel portion and a driver circuit for driving the pixel portion are formed over one substrate. At least a part of the driver circuit is formed using an inverted staggered thin film transistor in which an oxide semiconductor is used. The driver circuit as well as the pixel portion is provided over the same substrate, whereby manufacturing costs are reduced.

Abstract: A method is presented for reducing external resistance of a vertical field-effect-transistor (FET). The method includes forming a plurality of fins over a sacrificial layer disposed over a substrate, selectively removing the sacrificial layer to form an etch stop layer in direct contact with the substrate, disposing embedded bottom source/drain regions between a bottom portion of the plurality of fins and the etch stop layer, disposing encapsulation layers over the plurality of fins, recessing at least one of the encapsulation layers to expose top portions of the plurality of fins, forming top spacers adjacent the top portions of the plurality of fins, and forming top source/drain regions over the top portions of the plurality of fins.