Abstract: Methods, systems, and devices for access line formation for a memory array are described. The techniques described herein may be used to fabricate access lines for one or more decks of a memory array. In some examples, one or more access lines of a deck may be formed using an independent processing step. For example, different fabrication processes may be used to form a plurality of access lines in a deck and to form the pillars (e.g., the memory cells) that are coupled with the access lines. In some examples, an offset between the access lines and the pillars may exist due to the components being fabricated in different processing steps.

Abstract: A position-sensitive photodetector device includes a grid of series-connected photodetectors that are electrically coupled to either a vertical photodetector array (VA photodetectors) or to a horizontal photodetector array (HA photodetectors). The VA and HA photodetectors are arranged in an alternating sequence along rows and/or columns throughout the grid. A horizontal-position readout line is electrically coupled to a termination of each vertical photodetector array, and a vertical-position readout line is electrically coupled to a termination of each horizontal photodetector array.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC includes a first dielectric structure having first inner sidewalls over an interlayer dielectric (ILD) structure. A second dielectric structure is over the first dielectric structure, where the first inner sidewalls are between second inner sidewalls of the second dielectric structure. A sidewall barrier structure is over the first dielectric structure and extends vertically along the second inner sidewalls. A lower bumping structure is between the second inner sidewalls and extends vertically along the first inner sidewalls and vertically along third inner sidewalls of the sidewall barrier structure. An upper bumping structure is over both the lower bumping structure and the sidewall barrier structure and between the second inner sidewalls, where an uppermost point of the upper bumping structure is at or below an uppermost point of the second dielectric structure.

Abstract: A light source device includes a substrate, an electrode layer and an annular step-like surrounding frame both disposed on the substrate, a light emitter and a light detector both spaced apart from each other and mounted on the electrode layer in the surrounding frame, and a light permeable member disposed on the surrounding frame. The surrounding frame includes an upper tread arranged away from the substrate, an upper riser connected to an inner edge of the upper tread, a lower tread arranged at an inner side of the upper riser, and a lower riser connected to an inner edge of the lower tread and arranged away from the upper tread. The surrounding frame has a notch recessed in the lower tread and the lower riser for spatially communicating an inner side of the surrounding frame to an external space.

Abstract: Structural combinations of TIMs and methods of combining these TIMs in semiconductor packages are disclosed. An embodiment forms the structures by selectively metallizing a backside of a semiconductor chip (chip) on chip hot spots, placing a higher performance thermal interface material (TIM) on the metallized hot spots, selectively metalizing an underside of a lid in one or more metalized lid locations, and assembling a lid over the backside of the chip to create an assembly so that metalized lid locations are in contact with the higher performance TIMs. A lower performance TIM fills the region surrounding the higher performance TIM on the underside of the lid enclosing the chips. Disclosed are methods of disposing both solid and dispensable TIMs, curing and not curing the thermal interface, and structures to keep the TIMs in place while assembly the package and compressing dispensable TIMs.

Abstract: Described examples include an integrated circuit having a semiconductor substrate having an epitaxial layer located thereon, the epitaxial layer having a surface. The integrated circuit also has a buried layer formed in the semiconductor substrate, the epitaxial layer located between the buried layer and the surface. The integrated circuit also has a Schottky contact and an ohmic contact formed on the surface. The integrated circuit also has a Pdrift region in the epitaxial layer located between the ohmic contact and the Schottky contact.

Abstract: A semiconductor structure is provided. The semiconductor structure includes metallization structure, a plurality of conductive pads, and a dielectric layer. The plurality of conductive pads is over the metallization structure. The dielectric layer is on the metallization structure and covers the conductive pad. The dielectric layer includes a first dielectric film, a second dielectric film, and a third dielectric film. The first dielectric film is on the conductive pad. The second dielectric film is on the first dielectric film. The third dielectric film is on the second dielectric film. The a refractive index of the first dielectric film is smaller than a refractive index of the second dielectric film, and the refractive index of the second dielectric film is smaller than a refractive index of the third dielectric film.

Abstract: Disclosed is a photocoupler comprising: at least two lead frames; an optical channel structure including a light-emitting chip, a light-sensing chip, and a light-transmissive encapsulant body, wherein the light-emitting chip and the light-sensing chip are mounted and bonded on the lead frame and are coplanar, a light-emitting surface of the light-emitting chip and a light-sensing surface of the light-sensing chip face toward the same direction, the light-transmissive encapsulant body encloses the light-emitting chip and the light-sensing chip; and a light-reflecting package encloses the light-transmitting package, and all enclosing contact surface where the light-reflecting outer package contacts the light-transmissive encapsulant body is an optical reflective surface, wherein the light-reflecting encapsulant body and the light-transmissive encapsulant body are formed by double molding and epoxy molding, so that the light-transmissive encapsulant body and the light-reflecting encapsulant body are easy to be s

Abstract: A semiconductor device includes an n-type semiconductor substrate which includes an n-type impurity having a diffusion coefficient less than a diffusion coefficient of phosphorus, an n-type epitaxial layer which includes a high concentration region, an intermediate concentration region and a low concentration region formed in this order from the semiconductor substrate side and has a concentration gradient in which an n-type impurity concentration is decreased in a downward step-wise manner from the semiconductor substrate toward a crystal growth direction by the high concentration region, the intermediate concentration region and the low concentration region, and a trench structure which includes a trench formed in the low concentration region, an insulating layer formed on an inner wall of the trench and an embedded electrode which is embedded in the trench across the insulating layer.

Abstract: A light emitting diode display substrate, a manufacturing method thereof, and a display device are provided. The light emitting diode display substrate includes a base substrate; a light emitting diode located on the base substrate, and a self-assembled monolayer. The light emitting diode includes a graphene layer, and the graphene layer is located on a side of the light emitting diode close to the base substrate; the self-assembled monolayer is located between the graphene layer and the base substrate and connected with the graphene layer.

Abstract: An organic light-emitting display apparatus including: a substrate; a pixel electrode located on the substrate; a pixel-defining film coveting an end portion of the pixel electrode; an intermediate layer located on the pixel electrode and including an emission layer; a counter electrode located on the intermediate layer; a passivation layer located on the counter electrode and including a cover portion covering a top surface of the counter electrode and a protrusion extending from an end portion of the cover portion away from the substrate; and an encapsulation member covering the passivation layer.

Abstract: Fabricating a photonic integrated circuit includes fabricating structures in one or more silicon layers. At least a first silicon layer comprises: one or more photonic structures, where the photonic structures include one or more waveguides and one or more photodetectors, and one or more light absorbing structures, where at least some of the light absorbing structures include doped silicon. Fabricating the photonic integrated circuit also includes fabricating at least one waveguide in the photonic integrated circuit for receiving light into at least one of the silicon layers.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a semiconductor substrate, a plurality of first set conductive elements separately positioned above the semiconductor substrate, a plurality of insulating blocks respectively correspondingly positioned between adjacent pairs of the plurality of first set conductive elements, a plurality of first set supporting pillars respectively correspondingly positioned between adjacent pairs of the plurality of first set conductive elements and respectively correspondingly positioned over the plurality of insulating blocks, and a plurality of spaces respectively correspondingly positioned adjacent to the plurality of first set supporting pillars and respectively correspondingly positioned over the plurality of insulating blocks.

Abstract: A method for manufacturing an optical semiconductor device includes the steps of bonding a chip including a first substrate and a compound semiconductor layer disposed on the first substrate to a second substrate including silicon such that the compound semiconductor layer faces the second substrate; after the step of bonding the chip, etching the first substrate; after the etching step, forming a resist having a residue of the first substrate exposed therefrom and covering the compound semiconductor layer and the second substrate; and after the step of forming the resist, etching the residue.

Abstract: Disclosed are a structure of a quantum-dot light emitting device including a charge generation junction layer and a method of fabricating the quantum-dot light emitting device. A quantum-dot light emitting device according to an embodiment of the present invention includes a negative electrode, a first charge generation junction layer including a p-type semiconductor layer and an n-type semiconductor layer, a quantum-dot light emitting layer, a hole transport layer, a second charge generation junction layer including a p-type semiconductor layer and an n-type semiconductor layer, and a positive electrode. The first and second charge generation junction layers is formed using a solution process. Accordingly, charge generation and injection can be stabilized, a process time can be shorted, and problems in the work function a positive or a negative electrode of a quantum-dot light emitting device can be addressed.

Abstract: Tapered resistive memory devices with interface dipoles are provided. In one aspect, a ReRAM device includes: a bottom electrode; a core dielectric that is thermally conductive disposed on the bottom electrode; an oxide resistive memory cell disposed along outer sidewalls of the core dielectric, wherein the oxide resistive memory cell has inner edges adjacent to the core dielectric, and outer edges that are tapered; an outer coating disposed adjacent to the outer edges of the oxide resistive memory cell; and a top electrode disposed on the core dielectric, the oxide resistive memory cell, and the outer coating. A method of forming a ReRAM device as well as a method of operating a ReRAM device are also provided.

Abstract: A semiconductor device includes: a semiconductor chip including a substrate having a first surface and a second surface, which are opposite to each other; a through hole penetrating the substrate; a first conductive pad on the first surface of the substrate; a first bump formed over and electrically connected to the first conductive pad; a second conductive pad on the second surface of the substrate; a second bump formed over and electrically connected to the second conductive pad; and a connection electrode buried in the through hole, the connection electrode electrically connecting the first bump and the second bump.

Abstract: A vertical power semiconductor transistor device includes: a drain region of a first conductivity type; a body region of a second conductivity type; a drift region of the first conductivity type which separates the body region from the drain region; a source region of the first conductivity type separated from the drift region by the body region; a gate trench extending through the source and body regions and into the drift region, the gate trench including a gate electrode; and a field electrode in the gate trench or in a separate trench. The drift region has a generally linearly graded first doping profile which increases from the body region toward a bottom of the trench that includes the field electrode, and a graded second doping profile that increases at a greater rate than the first doping profile from an end of the first doping profile toward the drain region.

Abstract: A cover for an optoelectronic component includes a body of a first material, the body includes a lower side and, starting from the lower side, a recess for the optoelectronic component, the body includes a side surface adjacent to the lower side, the recess is continued as far as the side surface, a plate of a second material is arranged on the side surface, the second material being transparent for a radiation wavelength of the optoelectronic component, and the body and the plate are connected.

Abstract: An optoelectronic semiconductor component for the emission of multicolored radiation may have a multiplicity of active regions arranged next to one another. The active regions may be configured as microrods or nanorods and configured to generate primary electromagnetic radiation. A first group of the active regions may respectively be followed in an emission direction by a first luminescence conversion element, which is suitable for converting the primary radiation into first secondary radiation. A second group of the active regions is respectively followed in the emission direction by a second luminescence conversion element, which is suitable for converting the primary radiation into second secondary radiation. The primary radiation, the first secondary radiation, and the second secondary radiation having different colors.