Abstract: Provided is a semiconductor device. A semiconductor device includes a substrate, a buffer layer provided on the substrate, a semiconductor layer provided on the buffer layer, a body region provided at a part of a surface layer of the semiconductor layer, a source region provided at a part of a surface layer of the body region, a drain region provided at a part of the surface layer of the semiconductor layer outside the body region, a gate insulating layer provided to extend from the surface layer of the body region to a predetermined depth, a gate electrode provided on the gate insulating layer, a source electrode provided on the source region, a drain electrode provided on the drain region, and an isolation region provided to extend from the surface layer of the semiconductor layer to above the predetermined depth.

Abstract: A semiconductor device comprises: a lead-frame comprising a die pad having at least one electrically conductive die pad area an insulating layer applied onto the electrically conductive die pad area. An electrically conductive layer is applied onto the insulating layer with one or more semiconductor dice coupled, for instance adhesively, to the electrically conductive layer. The electrically conductive die pad area, the electrically conductive layer and the insulating layer sandwiched therebetween form at least one capacitor integrated in the device. The electrically conductive die pad area comprises a sculptured structure with valleys and peaks therein; the electrically conductive layer comprises electrically conductive filling material extending into the valleys in the sculptured structure of the electrically conductive die pad area.

Abstract: An integrated circuit package may be formed including at least one die side integrated circuit device having an active surface electrically attached to an electronic interposer, wherein the at least one die side integrated circuit device is at least partially encased in a mold material layer and wherein a back surface of the at least one die side integrated circuit device is in substantially the same plane as an outer surface of the mold material layer. At least one stacked integrated circuit device may be electrically attached to the back surface of the at least one die side integrated circuit through an interconnection structure formed between the at least one die side integrated circuit device and the at least one stacked integrated circuit device.

Abstract: Approaches for the metallization of solar cells and the resulting solar cells are described. In an example, a method of fabricating a solar cell involves forming a barrier layer on a semiconductor region disposed in or above a substrate. The semiconductor region includes monocrystalline or polycrystalline silicon. The method also involves forming a conductive paste layer on the barrier layer. The method also involves forming a conductive layer from the conductive paste layer. The method also involves forming a contact structure for the semiconductor region of the solar cell, the contact structure including at least the conductive layer.

Abstract: The application concerns a method of manufacturing optoelectronic semiconductor components (1) comprising the following steps: A) Growing a semiconductor layer sequence (3) for generating radiation onto a growth substrate (2), B) Structuring the semiconductor layer sequence (3) into emitter strands (11) so that the semiconductor layer sequence (3) is removed in gaps (12) between adjacent emitter strands (11), C) Applying a passivation layer (4), the semiconductor layer sequence (3) at waveguide contacts (51) remote from the growth substrate (2) and the gaps (12) remaining at least partially free, D) Producing at least one metal layer (50), which extends from the waveguide contacts (51) into the gaps (12), E) Replacing the growth substrate (2) with a carrier (6), F) Making vias (53) in the carrier (6) so that the metal layer (50) and underside contacts (52) of the semiconductor layer sequence (3) facing the carrier (6) are electrically contacted, and removing the carrier (6) between at least some of the emitt

Abstract: Unit cells of a current sensing portion are disposed in a sensing effective region of a main non-operating region. In a sensing non-operating region of the main non-operating region excluding the sensing effective region, an n?-type region that surrounds a periphery of the sensing effective region is disposed in a surface region of the front surface of the semiconductor substrate. In the main non-operating region, a p-type base region disposed in a surface region of the front surface of the semiconductor substrate opposes the sensing effective region across the n?-type region. The p-type base region is fixed at a source potential of the main semiconductor element 11. A field insulating film on the front surface of the semiconductor substrate is thicker at a portion that covers the n?-type region that in other portions.

Abstract: A display device is disclosed. In an embodiment a device includes at least one optoelectronic semiconductor component configured to generate primary radiation, a plurality of pixels, wherein each pixel includes at least a first subpixel configured to generate radiation in a first spectral range and a second subpixel configured to generate radiation in a second spectral range different from the first spectral range, wherein the first and second subpixels are each assigned an active region of the semiconductor component; and a radiation conversion element arranged downstream of at least some of the active regions, wherein the radiation conversion element configured to at least partially convert the primary radiation into a secondary radiation and to radiate the secondary radiation at a narrow angle.

Abstract: Embodiments of the present application relate to illumination devices using luminescent nanostructures. An illumination device includes a first conductive layer, a second conductive layer, a hole transport layer, an electron transport layer and a material layer that includes a plurality of luminescent nanostructures. The hole transport layer and the electron transport layer are each disposed between the first conductive layer and the second conductive layer. The material layer is disposed between the hole transport layer and the electron transport layer and includes one or more discontinuities in its thickness such that the hole transport layer and the electron transport layer contact each other at the one or more discontinuities. Resonant energy transfer occurs between the luminescent nanostructures and excitons at the discontinuities.

Abstract: A method for fabricating semiconductor device includes the steps of: forming an inter-metal dielectric (IMD) layer on a substrate; forming a metal interconnection in the IMD layer; forming a magnetic tunneling junction (MTJ) on the metal interconnection; forming a top electrode on the MTJ; and forming a trapping layer on the top electrode for trapping hydrogen. Preferably, the trapping layer includes a concentration gradient, in which a concentration of hydrogen decreases from a top surface of the top electrode toward the MTJ.

Abstract: A method is presented for incorporating a metal-ferroelectric-metal (MFM) structure in a cross-bar array in back end of the line (BEOL) processing. The method includes forming a first electrode, forming a ferroelectric layer in direct contact with the first electrode, forming a second electrode in direct contact with the ferroelectric layer, such that the first electrode and the ferroelectric layer are perpendicular to the second electrode to form the cross-bar array, and biasing the second electrode to adjust domain wall movement within the ferroelectric layer.

Abstract: A display device including a substrate; a sealing member surrounding a part of a transmission area of the substrate; a plurality of pixels in a display area of the substrate; an encapsulation substrate facing the substrate with the sealing member between the encapsulation substrate and the substrate; a transparent material layer between the substrate and the encapsulation substrate and corresponding to the transmission area; and a light-shielding portion on the encapsulation substrate and corresponding to the sealing member. A width of the light-shielding portion is greater than a width of the sealing member.

Abstract: [Object] To provide a solid-state imaging device and an electronic apparatus with further improved performance. [Solution] A solid-state imaging device including: a first substrate on which a pixel unit is formed, and a first semiconductor substrate and a first multi-layered wiring layer are stacked; a second substrate on which a circuit having a predetermined function is formed, and a second semiconductor substrate and a second multi-layered wiring layer are stacked; and a third substrate on which a circuit having a predetermined function is formed, and a third semiconductor substrate and a third multi-layered wiring layer are stacked. The first substrate, the second substrate, and the third substrate are stacked in this order. The pixel unit has pixels arranged thereon. The first substrate and the second substrate are bonded together with the first multi-layered wiring layer and the second semiconductor substrate opposed to each other.

Abstract: In some embodiments, integrated inductors may be built using processes for forming interconnects of semiconductor devices without requiring additional process steps. Integrated inductor coils may be formed by, for example, shunting an overlying electrically conductive material, such as, for example, bond pad metals (e.g., aluminum and alloys thereof), to an underlying electrically conductive material, such as, for example, an uppermost layer of wiring formed using Damascene processes (e.g., utilizing copper and alloys thereof), without vias to interconnect the two materials. In some embodiments, integrated inductors formed utilizing such processes may have a symmetric spiral design.

Abstract: A method for producing an optoelectronic component and an optoelectronic component are disclosed. In an embodiment a method includes providing a semiconductor chip having an active region for radiation emission, applying a seed layer on the semiconductor chip, wherein the seed layer includes a first metal and a second metal being different from the first metal, and wherein the second metal is less noble than the first metal, applying a structured photoresist layer directly to the seed layer and applying a solder layer at least to regions of the seed layer which are not covered by the photoresist layer, wherein a ratio of the first metal to the second metal in the seed layer is between 95:5 to 99:1.

Abstract: A display module includes a base substrate including an upper surface where a display area and a non-display area are defined, a lower surface, and a plurality of side surfaces, a circuit element layer including a planarization layer, a pixel defining layer defining an opening portion that overlaps the display area and exposes a portion of the planarization layer, a display element layer including a first electrode disposed on the planarization layer exposed by the opening part, a light emitting layer, and a second electrode, and a sealing layer disposed on the display element layer. A dam hole is defined, which is adjacent to an edge where two side surfaces of the side surfaces are connected in a plan view of the base substrate, overlaps the non-display area, and penetrates at least one of the planarization layer and the pixel defining layer.

Abstract: A display substrate, a manufacturing method and a display device are disclosed. The display substrate includes a base substrate, and a light-shielding layer and a plurality of light-emitting units arranged at a display region of the base substrate. A plurality of imaging pin-holes is formed in the light-shielding layer, an orthogonal projection of each imaging pin-hole onto the base substrate does not overlap an orthogonal projection an active light-emitting region of the corresponding light-emitting unit onto the base substrate, and at least a part of a surface of the light-shielding layer adjacent to the light-emitting units is uneven.

Abstract: The present invention provides a magnetoresistance effect element which has a high thermal stability factor ? and in which a magnetization direction of a recording layer is a perpendicular direction with respect to a film surface, and a magnetic memory including the same. Magnetic layers of a recording layer of the magnetoresistance effect element are divided into at least two, and an Fe composition with respect to a sum total of atomic fractions of magnetic elements in each magnetic layer is changed before stacking the magnetic layers.

Abstract: A semiconductor device includes a first conductivity type semiconductor layer having a first surface and a second surface opposite to the first surface and having an element portion formed in the first surface and an outer peripheral portion surrounding the element portion, a semiconductor element structure formed in the element portion, multiple guard ring trenches formed in the outer peripheral portion and each formed in the first surface of the semiconductor layer, and a second conductivity type outer peripheral portion impurity region formed in the outer peripheral portion, in which the multiple guard ring trenches include a first unit consisting of multiple guard ring trenches and a second unit consisting of multiple guard ring trenches arranged on the outside of the semiconductor layer relative to the multiple guard ring trenches belonging to the first unit, and in which the outer peripheral portion impurity region includes a first portion arranged below the multiple guard ring trenches belonging to the

Abstract: An HEMT includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer and the second III-V compound layer are different from each other. A source electrode and a drain electrode are disposed on the second III-V compound layer. The gate electrode is disposed on the second III-V compound layer between the source electrode and the drain electrode. An insulating layer is disposed between the drain electrode and the gate electrode and covers the second III-V compound layer. At least one electrode is disposed on the insulating layer and contacts the insulating layer, wherein a voltage is applied to the electrode.

Abstract: According to one embodiment, the oxide semiconductor layer contains at least one of indium (In) and tin (Sn). The insulating film is provided between the control electrode and the oxide semiconductor layer, and contains silicon oxide. The metal oxide film is provided between the insulating film and the oxide semiconductor layer, and contacts the insulating film and the oxide semiconductor layer. The metal oxide film contains at least one selected from a group consisting of gallium (Ga), tungsten (W), germanium (Ge), aluminum (Al), molybdenum (Mo), and titanium (Ti).