Abstract: Provided are an organic light-emitting display panel and manufacturing method thereof, a display device and a mask. The organic light-emitting display panel includes: multiple organic light-emitting units, a photosensitive module setting area, a display area surrounding the photosensitive module, and a bezel area surrounding the display area. The display area includes a first display area and a second display area. Organic light-emitting units in the first display area share a first cathode. Organic light-emitting units in the same group in the second display area share a second cathode. Two adjacent second cathodes are separated by a first gap. The bezel area extends to the photosensitive module setting area by the first gap.

Abstract: In described examples, a circuit (e.g., an integrated circuit) includes a semiconductor substrate that includes a frontside surface and a backside surface. A circuit element is included at the frontside surface. An optional electrical insulator layer can be included adjacent to the backside surface. A distributor layer is included adjacent to the backside surface. In some examples, the distributor layer includes a distributor material that includes a matrix of cohered nanoparticles and metallic particles embedded by the cohered nanoparticles.

Abstract: The present invention relates to a micro LED structure and a method of manufacturing the same that facilitate realizing of pixels of the micro LED structure.

Abstract: Instead of discrete LED chips, monolithic LED strips reduce manufacturing time and inaccuracy when building high-resolution displays with small LED pixels of less than 100 micrometers. Guide strips next to LED strips align the monolithic LED strips and increase light emission area. A monolithic LED strip formed on a substrate has a P contact and an N contact. A first transfer layer is on an upper surface of the monolithic LED strip. The first transfer layer separates the monolithic LED strip from the substrate. A second transfer layer applied to the lower surface of the monolithic LED strip separates the monolithic LED strip from the first transfer layer. A display backplane is prepared with positive electrodes, negative electrodes, positive contact pads, and negative contact pads.

Abstract: A semiconductor module includes a base substrate; a plurality of light emitting elements; a plurality of color conversion layers being in contact with each upper portion of the plurality of light emitting elements adjacent to each other; and a light shielding layer disposed between the plurality of light emitting elements adjacent each other and between the color conversion layers adjacent to each other, and separating the plurality of light emitting elements and a plurality of color conversion layers.

Abstract: An optoelectronic device includes an emitter of light rays and a receiver of light rays. The emitter is encapsulated within a first encapsulation layer, and the receiver is encapsulated within a second encapsulation layer. An opaque layer covers the first encapsulation layer (encapsulating the receiver) and covers the second encapsulation layer (encapsulating the emitter). The first and second encapsulation layers are separated by a region of opaque material. This opaque material may be provided by the opaque layer or an opaque fill.

Abstract: A power semiconductor module includes a power semiconductor die attached to the first metallized side, a passive component attached to the first metallized side, a first isolation layer encapsulating the power semiconductor die and the passive component, a first structured metallization layer on the first isolation layer, and a first plurality of electrically conductive vias extending through the first isolation layer from the first structured metallization layer to the power semiconductor die and the passive component.

Abstract: A nitride semiconductor device includes a nitride semiconductor layer, channel cells in the nitride semiconductor layer, a source lead region of a second conductivity type in the nitride semiconductor layer, and a source electrode on a side where a first main surface of the nitride semiconductor layer is located. The channel cells each include a well region of a first conductivity type and a source region of the second conductivity type in contact with the well region. The source lead region is connected to the source region. The channel cells extend in a first direction in a planar view from a normal direction of the first main surface, and arranged in a second direction intersecting with the first direction in the planar view. The source electrode is in contact with the source lead region away from a line of the channel cells arranged in the second direction.

Abstract: A work shoe, in particular a safety shoe, includes at least one passive protection unit which is intended to passively protect a shoe wearer at least against mechanical and/or electrical loads, and includes at least one active protection unit which has at least one sensor unit which is intended to detect at least one characteristic variable at least in order to enable a protection function and/or a comfort function. The sensor unit is configured at least for detecting at least one person-related characteristic variable and/or at least one environmental characteristic variable.

Abstract: An optoelectronic semiconductor device and a method for manufacturing an optoelectronic semiconductor device are disclosed. In an embodiment, an optoelectronic semiconductor device includes a semiconductor body having an active region configured to generate electromagnetic radiation and a coupling-out surface along a main radiation direction, and a wavelength conversion element having conversion regions, the conversion regions optically separated from one another by metallic separators, wherein the wavelength conversion element is arranged downstream of the semiconductor body in the main radiation direction of the active region, wherein the active region comprises a plurality of independently controllable emission regions, and wherein the emission regions are at least partially aligned with the conversion regions and explicitly assigned to the conversion regions.

Abstract: An optoelectronic semiconductor device includes a semiconductor layer sequence including an active zone that generates radiation by electroluminescence; a p-electrode and an n-electrode; an electrically insulating passivation layer on side surfaces of the semiconductor layer sequence; and an edge field generating device on the side surfaces on a side of the passivation layer facing away from the semiconductor layer sequence at the active zone, wherein the edge field generating device is configured to generate an electric field at least temporarily in an edge region of the active zone so that, during operation, a current flow through the semiconductor layer sequence is controllable in the edge region.

Abstract: A semiconductor device includes a source structure, a bit line, a stacked structure between the source structure and the bit line, a source contact structure penetrating the stacked structure and electrically coupled to the source structure, and a protective pattern interposed between the source contact structure and the source structure and having a varying thickness depending on an area of the protective pattern.

Abstract: A semiconductor device includes a semiconductor body having first and second opposing surfaces, an active area including active transistor cells, and an edge termination region laterally surrounding the active area. Each active transistor cell includes a mesa and a columnar trench having a field plate. The edge termination region includes inactive cells each including a columnar termination trench having a field plate, and a termination mesa including a drift region of a first conductivity type. The edge termination region includes a transition region laterally surrounding the active region and an outer termination region laterally surrounding the transition region. In the transition region, the termination mesa includes a body region of a second conductivity type arranged on the drift region. In the outer termination region, the drift region extends to the first surface. A buried doped region of the edge termination region is positioned in the transition and outer termination regions.

Abstract: A split gate power device is disclosed having a trench containing a U-shaped gate that, when biased above a threshold voltage, creates a conductive channel in a p-well. Below the gate is a field plate in the trench, coupled to the source electrode, for spreading the electric field along the trench to improve the breakdown voltage. The top gate poly is initially formed relatively thin so that it can be patterned using non-CMP techniques, such as dry etching or wet etching. As such, the power device can be fabricated in conventional fabs not having CMP capability. In one embodiment, the thin gate has vertical and lateral portions that create conductive vertical and lateral channels in a p-well. In another embodiment, the thin gate has only vertical portions along the trench sidewalls for minimizing surface area and gate capacitance.

Abstract: Display tiles comprising pixel elements on a first surface of a substrate connected by an electrode, a driver located opposite the first surface, and a connector wrapped around an edge surface of the substrate connecting the driver to the pixel elements. Displays comprised of display tiles and methods of manufacturing display tiles and displays are also disclosed.

Abstract: Methods, systems, and devices for access line formation for a memory array are described. The techniques described herein may be used to fabricate access lines for one or more decks of a memory array. In some examples, one or more access lines of a deck may be formed using an independent processing step. For example, different fabrication processes may be used to form a plurality of access lines in a deck and to form the pillars (e.g., the memory cells) that are coupled with the access lines. In some examples, an offset between the access lines and the pillars may exist due to the components being fabricated in different processing steps.

Abstract: A position-sensitive photodetector device includes a grid of series-connected photodetectors that are electrically coupled to either a vertical photodetector array (VA photodetectors) or to a horizontal photodetector array (HA photodetectors). The VA and HA photodetectors are arranged in an alternating sequence along rows and/or columns throughout the grid. A horizontal-position readout line is electrically coupled to a termination of each vertical photodetector array, and a vertical-position readout line is electrically coupled to a termination of each horizontal photodetector array.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC includes a first dielectric structure having first inner sidewalls over an interlayer dielectric (ILD) structure. A second dielectric structure is over the first dielectric structure, where the first inner sidewalls are between second inner sidewalls of the second dielectric structure. A sidewall barrier structure is over the first dielectric structure and extends vertically along the second inner sidewalls. A lower bumping structure is between the second inner sidewalls and extends vertically along the first inner sidewalls and vertically along third inner sidewalls of the sidewall barrier structure. An upper bumping structure is over both the lower bumping structure and the sidewall barrier structure and between the second inner sidewalls, where an uppermost point of the upper bumping structure is at or below an uppermost point of the second dielectric structure.

Abstract: A light source device includes a substrate, an electrode layer and an annular step-like surrounding frame both disposed on the substrate, a light emitter and a light detector both spaced apart from each other and mounted on the electrode layer in the surrounding frame, and a light permeable member disposed on the surrounding frame. The surrounding frame includes an upper tread arranged away from the substrate, an upper riser connected to an inner edge of the upper tread, a lower tread arranged at an inner side of the upper riser, and a lower riser connected to an inner edge of the lower tread and arranged away from the upper tread. The surrounding frame has a notch recessed in the lower tread and the lower riser for spatially communicating an inner side of the surrounding frame to an external space.

Abstract: Structural combinations of TIMs and methods of combining these TIMs in semiconductor packages are disclosed. An embodiment forms the structures by selectively metallizing a backside of a semiconductor chip (chip) on chip hot spots, placing a higher performance thermal interface material (TIM) on the metallized hot spots, selectively metalizing an underside of a lid in one or more metalized lid locations, and assembling a lid over the backside of the chip to create an assembly so that metalized lid locations are in contact with the higher performance TIMs. A lower performance TIM fills the region surrounding the higher performance TIM on the underside of the lid enclosing the chips. Disclosed are methods of disposing both solid and dispensable TIMs, curing and not curing the thermal interface, and structures to keep the TIMs in place while assembly the package and compressing dispensable TIMs.