Patents Examined by Robert P. Limanek
  • Patent number: 5581126
    Abstract: An SRAM array configuration includes even bitline pairs which each laterally interchange at a crossover placed at the 1/2 point along the length of the bitline pairs, and which SRAM array includes odd bitline pairs which each laterally interchange at each of two associated crossovers at the 1/4 and 3/4 points along the length of the bitline pairs. Consequently, signals or noise resident on neighboring bitline pairs or other neighboring conductive structure couple a common-mode voltage onto a given bitline pair through lateral parasitic capacitance to the neighboring conductive structure. Such a common-mode noise signal does not affect the differential signal on the given bitline pair. This interlaced configuration is useful for one or more pairs of differential signal lines, whether used within an SRAM array or for global interconnect between circuit blocks.
    Type: Grant
    Filed: September 14, 1995
    Date of Patent: December 3, 1996
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Jerry D. Moench
  • Patent number: 5581107
    Abstract: An object of the present invention is to ease the dielectric strength requirements for transistors forming power supply circuits or the like. A nonvolatile semiconductor memory of the present invention includes a plurality of memory cells, each of which is composed of a floating gate, a control gate, a drain, and a source, and a negative voltage generating means whose generated negative voltage is applied to the control gate for drawing a charge stored in the floating gate into a channel or the source when stored data is erased electrically. The nonvolatile memory of the present invention further includes positive erasure voltage generating means, and a positive voltage higher than a conventional supply voltage generated by the positive erasure voltage generating means is applied to the channel or the source.
    Type: Grant
    Filed: December 14, 1994
    Date of Patent: December 3, 1996
    Assignee: Fujitsu Limited
    Inventors: Shouichi Kawamura, Nobuaki Takashina, Yasushi Kasa, Kiyoshi Itano
  • Patent number: 5581110
    Abstract: A trench which has walls intersecting a surface of a semiconductor substrate and an oxidation/diffusion barrier layer lining the walls is disclosed. The oxidation/diffusion barrier extends over the edges of the trench to prevent, for example, stress defects in the trench corners and vertical bird's beak formation within the trench. A filler material such as polysilicon is deposited within the trench followed by the deposition of a planarizing layer over the trench. After heat is applied, the planarizing layer flows to form a planarized layer over the trench. Using high pressure and phosphosilicate glass for the planarizing layer, the planarizing layer flows appropriately at low temperatures for short times.
    Type: Grant
    Filed: August 17, 1995
    Date of Patent: December 3, 1996
    Assignee: National Semiconductor Corporation
    Inventors: Reda R. Razouk, Kulwant S. Egan, Wipawan Yindeepol, Waclaw C. Koscielniak
  • Patent number: 5581117
    Abstract: The present invention provides an Si base semiconductor monocrystal substrate which includes an Si(11n) substrate where n=1.5-2.5. An intermediate layer is formed on the Si(11n) substrate. The intermediate layer is made of a material selected from the group consisting of ZnTe and Zn-rich CdZnTe, The intermediate layer has a thickness in the range of 50-200 angstroms. The intermediate layer is oriented in a (11n')B plane. An upper layer is formed on the intermediate layer. The upper layer is made of a material selected from the group consisting of CdTe and Cd-rich CdZnTe. The upper layer is oriented in a (11n")B plane. The indexes n' and n" satisfy the following equations. ##EQU1## where y is the lattice mismatch between the Si substrate and the intermediate layer. ##EQU2## where y' is the lattice mismatch between the Si substrate and the upper layer.
    Type: Grant
    Filed: December 13, 1995
    Date of Patent: December 3, 1996
    Assignee: NEC Corporation
    Inventor: Masaya Kawano
  • Patent number: 5581112
    Abstract: A lateral bipolar transistor comprising a self-aligned polysilicon base contact, and polysilicon emitter and collector contacts is provided. The self-aligned base contact significantly reduces the base width and therefore the base resistance compared with conventional lateral bipolar transistors, thus improving f.sub.t and f.sub.max. The polysilicon emitter and collector contacts improve the emitter efficiency and current gain, and allows for more flexible contact placement. The process is compatible with conventional double-poly bipolar processes.
    Type: Grant
    Filed: October 23, 1995
    Date of Patent: December 3, 1996
    Assignee: Northern Telecom Limited
    Inventors: Xiao-Ming Li, Sorin P. Voinigescu
  • Patent number: 5578859
    Abstract: A semiconductor structure having one or a plurality of lateral, high-blocking semiconductor components in a semiconductor of a metalized substrate (2), a dielectric layer (3) contiguous to the substrate, a homogeneously doped drift zone (4) disposed above the dielectric layer, and having heavily-doped zones of the semiconductor components which are formed in or extend into the drift zone and are electrically contacted. At least the zones (5, 6) of the semiconductor components, which can have a high potential difference with respect to the substrate during operational functioning mode of the semiconductor components, extend up to the dielectric layer (3).
    Type: Grant
    Filed: July 18, 1994
    Date of Patent: November 26, 1996
    Assignee: Daimler-Benz AG
    Inventors: Wolfgang Wondrak, Raban Held, Erhard Stein, Horst Neubrand
  • Patent number: 5578836
    Abstract: An antifuse according to the present invention includes a lower electrode formed from a first metal interconnect layer in an integrated circuit or the like. The lower electrode is disposed on an insulating surface. An inter-metal dielectric including an antifuse aperture disposed there lies over the inter-metal dielectric layer. The antifuse aperture extends through the inter-metal dielectric layer and also extends completely through the lower electrode. An antifuse material is disposed in the antifuse aperture. An upper electrode formed from a first metal interconnect layer is disposed over the antifuse material.
    Type: Grant
    Filed: November 14, 1994
    Date of Patent: November 26, 1996
    Assignee: Actel Corporation
    Inventors: John D. Husher, Abdul R. Forouhi
  • Patent number: 5578846
    Abstract: An improved ferroelectric FET structure in which the ferroelectric layer is doped to reduce retention loss. A ferroelectric FET according to the present invention includes a semiconductor layer having first and second contacts thereon, the first and second contacts being separated from one another. The ferroelectric FET also includes a bottom electrode and a ferroelectric layer which is sandwiched between the semiconductor layer and the bottom electrode. The ferroelectric layer is constructed from a perovskite structure of the chemical composition ABO.sub.3 wherein the B site comprises first and second elements and a dopant element that has an oxidation state greater than +4 in sufficient concentration to impede shifts in the resistance measured between the first and second contacts with time. The ferroelectric FET structure preferably comprises Pb in the A-site. The first and second elements are preferably Zr and Ti, respectively.
    Type: Grant
    Filed: March 17, 1995
    Date of Patent: November 26, 1996
    Inventors: Joseph T. Evans, Jr., William L. Warren, Bruce A. Tuttle
  • Patent number: 5578873
    Abstract: An integrated circuit includes: a) a semiconductor substrate; b) a first conductivity type substrate diffusion region within the semiconductor substrate, the first conductivity type substrate diffusion region being electrically conductive and having an outer first total area; c) a thin film polysilicon layer of the first conductivity type overlying and being in ohmic electrical connection with the substrate diffusion region; and d) a pillar of electrically conductive material extending outwardly from the thin film polysilicon layer over the electrically conductive diffusion region, the pillar having a total cross sectional second area where the pillar joins the thin film polysilicon layer, the second area being less than the first area and being received entirely within the confines of the first area.
    Type: Grant
    Filed: May 22, 1995
    Date of Patent: November 26, 1996
    Assignee: Micron Technology, Inc.
    Inventor: Monte Manning
  • Patent number: 5578848
    Abstract: High quality, ultra thin SiO.sub.2 /Si.sub.3 N.sub.4 (ON) dielectric layers have been fabricated by in situ multiprocessing and low pressure rapid-thermal N.sub.2 O-reoxidation (LRTNO) of Si.sub.3 N.sub.4 films. Si.sub.3 N.sub.4 film was deposited on the RTN-treated polysilicon by rapid-thermal chemical vapor deposition (RT-CVD) using SiH.sub.4 and NH.sub.3, followed by in situ low pressure rapid-thermal reoxidation in N.sub.2 O (LRTNO) or in O.sub.2 (LRTO) ambient. Results show that ultra thin (T.sub.ox,eq =.about.29 .ANG.) ON stacked film capacitors with LRTNO have excellent electrical properties, and reliability.
    Type: Grant
    Filed: September 18, 1995
    Date of Patent: November 26, 1996
    Assignee: Regents of the University of Texas System
    Inventors: Dim-Lee Kwong, Giwan Yoon, Jonghan Kim, Liang-Kai Han, Jiang Yan
  • Patent number: 5578857
    Abstract: In accordance with the invention, a double poly process is used to double the memory density of a buried bit line ROM on the same silicon area. In particular the word-line pitch is decreased to increase the cell density in a direction perpendicular to the word lines. The invention uses a self-aligned method for ROM code implantation and a polyplanarization by chemical-mechanical polishing (CMP) to achieve a self aligned double poly word line structure.
    Type: Grant
    Filed: December 5, 1994
    Date of Patent: November 26, 1996
    Assignee: United Microelectronics Corporation
    Inventors: Gary Hong, Ming-Tzong Yang, Chen-Chiu Hsue
  • Patent number: 5576569
    Abstract: An improved structure and process of fabricating a programmable and erasable read only memory device wherein a thick oxide region is formed on the surface of a semiconductor substrate. The thick oxide region is removed forming a depression in the surface. Impurity ions are implanted into the depression forming a lightly doped source region. A tunnel oxide layer is formed on the substrate surface. Next, the floating gate layer is formed on the tunnel oxide layer which at least partially overlies the lightly doped source region. A gate isolation layer and control gate layer are formed over the floating gate layer. Subsequently, the source and drain regions are formed in the substrate on opposite sides of the gate structure. A dielectric layer is formed over the control gate region and substrate. Contact opening are formed. Electrical contacts and metallurgy lines with appropriate passivation are formed that connect the source, drain and gate elements to form an electrical programmable memory device.
    Type: Grant
    Filed: April 24, 1995
    Date of Patent: November 19, 1996
    Assignee: United Microelectronics Corporation
    Inventors: Sheng-Hsing Yang, Jyn-Kuang Lin
  • Patent number: 5576566
    Abstract: A semiconductor trench capacitor structure having a first level aligned isolation structure and buried strap that extends from within the trench into the doped semiconductor substrate. The semiconductor trench capacitor structure may be fabricated by forming a shallow trench within the trench capacitor and semiconductor substrate, depositing a layer of conductive material within the shallow trench, using a mask to define and recess the strap and depositing insulating material within the shallow trench.
    Type: Grant
    Filed: April 13, 1995
    Date of Patent: November 19, 1996
    Assignee: International Business Machines Corporation
    Inventor: Donald M. Kenney
  • Patent number: 5576554
    Abstract: A system for substrate scale integration by interconnecting a large number of separate memory (or other circuit) modules on a semiconductor substrate so as to electrically exclude both defective modules and defective interconnect/power segments, and include operative modules and interconnect/power segments. A set of discretionary connections are associated with each of the separate modules and interconnect/power segments and such connections are made (or broken) after a module or interconnect or power segment is tested. A power supply network is set up by combining operative power segments. A bidirectional bus is set up by combining operative interconnect segments to connect to each operative modules. This bidirectional bus consists of one or more hierarchies for speed, power and yield considerations. Each module is assigned an identity code using discretionary connections.
    Type: Grant
    Filed: December 10, 1993
    Date of Patent: November 19, 1996
    Assignee: Monolithic System Technology, Inc.
    Inventor: Fu-Chieh Hsu
  • Patent number: 5576564
    Abstract: The present invention provides a substrate providing a ferroelectric crystal thin film which includes an electrode formed on a semiconductor single crystal substrate and a ferroelectric crystal thin film of Bi.sub.4 Ti.sub.3 O.sub.12 formed on the electrode through the intermediary of a buffer layer.
    Type: Grant
    Filed: December 28, 1994
    Date of Patent: November 19, 1996
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Sakiko Satoh, Hironori Matsunaga, Kenji Nakanishi, Yoshiyuki Masuda, Masayoshi Koba
  • Patent number: 5574314
    Abstract: A semiconductor device including a metal base; a first ceramic frame bonded to the metal base; a metallization layer for I/O terminals disposed on the first ceramic frame; a second ceramic frame larger than the first ceramic frame and bonded to the first ceramic frame and to the metallization layer; a metal disposed on and covering inner side walls of the first and second ceramic frames, not electrically contacting the metallization layer but electrically contacting the base member; a semiconductor element disposed on the base member within the first ceramic frame, having I/O terminals connected to the metallization layer, and having a grounding terminal connected to the base member; and a cover hermetically sealing the semiconductor element, bonded to the second ceramic frame, and electrically connected to the metal disposed on the inner side walls.
    Type: Grant
    Filed: July 17, 1995
    Date of Patent: November 12, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Masaaki Okada, Tosio Usuki
  • Patent number: 5572063
    Abstract: A bipolar transistor is provided in which the emitters do not traverse the base but terminate inside the top surface of the base. Each emitter is L-shaped in some embodiments. The base top surface has a polygonal or circular outer boundary. The transistor has a long emitter perimeter available for base current flow and more than two emitter sides (e.g., five sides) available for base current flow. Further, the transistor has a large ratio of the emitter area to the base area. Consequently, the transistor has low noise, high gain, high frequency range, and a small size.
    Type: Grant
    Filed: October 13, 1994
    Date of Patent: November 5, 1996
    Assignee: National Semiconductor Corporation
    Inventor: Ali A. Iranmanesh
  • Patent number: 5572056
    Abstract: A ROM is formed by depositing a first layer composed of a material selected from polysilicon and polycide on the substrate, patterning the first layer by masking and etching, depositing a dielectric layer over the first layer and patterning the dielectric layer and the first layer into the pattern of first conductor lines, forming a contact window through the dielectric layer down to the substrate, depositing a second layer composed of a material selected from polysilicon and polycide on the device and forming second conductor lines directed orthogonally to the first conductor lines formed from the first layer, and ion implanting into the substrate through the second layer to form a contact region electrically connected to the second conductor lines of the second layer.
    Type: Grant
    Filed: December 29, 1994
    Date of Patent: November 5, 1996
    Assignee: United Microelectronics Corporation
    Inventors: Chen-Chiu Hsue, Ming-Tzong Yang, Te-Sun Wu
  • Patent number: 5572067
    Abstract: An integrated circuit chip die (12) is manufactured with sacrificial structures (16) placed at the areas of die that are likely to experience cracks. According to one embodiment of the invention, these sacrificial structures are placed at the corners of the die. The sacrificial structures are constructed with metal lines (22, 24) that resist propagation of cracks into the area of the die containing electronic devices. The metal lines form lattice steps so that the surface of the die will more tightly bond to the molding compound that makes up the die package.
    Type: Grant
    Filed: October 6, 1994
    Date of Patent: November 5, 1996
    Assignee: Altera Corporation
    Inventor: Guru Thalapaneni
  • Patent number: 5569962
    Abstract: An SRAM semiconductor device comprises a first layer, a second layer and a third layer of polysilicon are separated by dielectric layers formed on a substrate, and a split gate structure with transistors formed in different polysilicon levels. Preferably, the split gate structure includes pull down transistors and pass gate transistors formed in different polysilicon levels; the second polysilicon layer extends into contact with the substrate; the second polysilicon layer contacts the third polysilicon layer in an interconnection region; and the third polysilicon layer comprises a polysilicon load resistor.
    Type: Grant
    Filed: November 16, 1994
    Date of Patent: October 29, 1996
    Assignee: United Microelectronics Corporation
    Inventor: Ming-Tzong Yang