Patents Examined by Rolf Hille
  • Patent number: 5614758
    Abstract: A self-aligned fully-walled monocrystalline silicon emitter-base structure for a bipolar transistor and methods for producing the structure are provided. The methods involve creating an oxide side wall surrounding a monocrystalline silicon emitter-base structure by first defining the emitter region in a base island region. Successive oxide layers are deposited on top of the emitter region and etched back to produce an oxide wall around the entire perimeter of the emitter region. In a preferred embodiment of the invention a metal silicide is also formed across the top of the base island region of the semiconductor outside of the emitter region. Since the extrinsic base region, outside of the oxide sidewalls, is entirely covered by a low resistance silicide film, the base contact area can be significantly reduced compared to prior art devices.The process results in a fully-walled emitter-base structure made of monocrystalline silicon which exhibits improved high-frequency performance.
    Type: Grant
    Filed: August 29, 1994
    Date of Patent: March 25, 1997
    Assignee: Hewlett-Packard Company
    Inventor: Francois Hebert
  • Patent number: 5585671
    Abstract: A flip-chip IC package (10) provides a thermally-conductive lid (20) attached to a backside of the chip (12) by a die attach layer (18) of a predetermined thickness range. A rim (22), preferably KOVAR iron-nickel alloy, is formed on the lid (20) with a depth (44) less than a sum (42) of a thickness of the chip, the interconnects (16), and a minimum final thickness (40) of the die attach layer (18) by a predetermined margin (46). An initial thickness of thermally-filled epoxy is applied to the backside of the chip and a layer of lid attach epoxy (24) is applied to the rim of the lid in a thickness sufficient to span the predetermined margin. The lid is floated on the die attach layer (18) with the rim of the lid surrounding the chip and floating on the lid attach material. The lid is clamped against the chip with a force sufficient to compress the die attach material to a predetermined thickness in a range less than the initial thickness and not less than the minimum final thickness (40).
    Type: Grant
    Filed: October 7, 1994
    Date of Patent: December 17, 1996
    Inventors: Voddarahalli K. Nagesh, Kim H. Chen, Cheng-Cheng Chang, Bahram Afshari, Jacques Leibovitz
  • Patent number: 5567987
    Abstract: The invention relates to a wiring structure for a semiconductor device and a method for manufacturing the same, which fills up a contact hole of below one half micron. An insulating layer is formed on a semiconductor substrate, and a contact hole is formed in the insulating layer. On the insulating layer, a first metal is deposited via a CVD method to form a CVD metal layer or a CVD metal plug filling up the contact hole. Then, the thus-obtained CVD metal layer or the CVD metal plug is heat-treated in a vacuum at a high temperature below the melting point of the first metal, thereby planarizing the surface of the CVD metal layer. A second metal is deposited via a sputtering method on the CVD metal layer or on the CVD metal plug to thereby form a sputtered metal layer. The contact hole is filled up with the first metal by the CVD method and then a reliable sputtered metal layer is deposited via a sputtering method. The wiring layer can be used for semiconductor devices of the next generation.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: October 22, 1996
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Sang-in Lee
  • Patent number: 5561324
    Abstract: The present invention relates to a semiconductor device which comprises a semiconductor chip mounting section having a through hole, a radiating plate attached to one surface of the semiconductor chip mounting section so as to cover the through hole of the semiconductor chip mounting section, a semiconductor chip mounting plate which is formed within the through hole and mounted on the radiating plate, a surface of the semiconductor chip mounting plate, which is opposite to another surface thereof mounted on the radiating plate, being plated with gold, and the semiconductor chip mounting plate having improved electrical insulation properties and high thermal conductivity, and a semiconductor chip formed within the through hole and attached to the semiconductor chip mounting plate by a conductive adhesive.
    Type: Grant
    Filed: March 23, 1995
    Date of Patent: October 1, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Kozono, Shigeki Sako, Hiromichi Sawaya
  • Patent number: 5559363
    Abstract: A high-frequency, high-power, semiconductor device chip is impedance matched to an off-chip impedance by a matching network including a dielectric element located on a substrate ground plane portion adjacent to the device to be matched. A thin film dielectric layer is formed over the dielectric element, the semiconductor device and the surrounding substrate. A patterned metal matching circuit is disposed over the dielectric layer and is in electrical contact with an electrode of the high-frequency, high-power, semiconductor device. An impedance matching network is formed by the patterned metal circuit, the dielectric element, the dielectric layer and the underlying grounded substrate. The matching characteristics of the network can be tailored by selecting suitable dielectric materials for the dielectric element and by altering design of the patterned metal circuit.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: September 24, 1996
    Assignee: Martin Marietta Corporation
    Inventor: Anthony A. Immorlica, Jr.
  • Patent number: 5559369
    Abstract: A plastic encapsulated integrated circuit package is disclosed which comprises a multilayer ground plane assembly bonded to a lead frame with an integrated circuit die bonded to the composite assembly. The multilayer ground plane assembly is first formed by bonding together a metal sheet, such as a copper sheet, and a thermally conductive insulating layer, such as a thermally conductive polyimide material, to which is also bonded a layer of a b-stage adhesive material. The ground plane assembly may be bonded to the lead frame by placing the b-stage adhesive layer of the ground plane assembly against the lead frame and heating the ground plane assembly and lead frame to a temperature of from about 120.degree. C. to just under 200.degree. C. for a time period not exceeding about 10 seconds to bond the b-stage adhesive layer to the lead frame without oxidizing the lead frame.
    Type: Grant
    Filed: May 23, 1995
    Date of Patent: September 24, 1996
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Robert A. Newman
  • Patent number: 5557139
    Abstract: The transistor comprises a buried base P region, a buried emitter N+ region with elongate portions (fingers), deep contact P+ base regions, emitter N+ interconnection regions serving balancing resistor functions, and base, emitter, and collector surface contact electrodes. To provide a higher current gain and a larger safe operation area, with each emitter "finger" there are associated a screening P region interposed between the "finger" and a part of the respective N+ interconnection region, and a contact N+ region which extends to the "finger" and is surface connected to the screening P region by a dedicated electrode.
    Type: Grant
    Filed: June 28, 1994
    Date of Patent: September 17, 1996
    Assignee: Consorzio per la Ricerca Sulla Microelettronica nel Mezzogiorno
    Inventor: Sergio Palara
  • Patent number: 5557142
    Abstract: A shielded semiconductor package and a method for manufacturing the package is provided. The shielded semiconductor package comprises a metal coating (19) applied over an encapsulated semiconductor device (16). The device may be transfer molded or encapsulated by glob top technology. The metal coating (19) serves as a barrier to the transmission of electromagnetic or radio frequency energy, thereby shielding the semiconductor device (16). The shielded semiconductor package is manufactured by providing a metallization pattern (12 and 14) on a substrate (10) and mechanically attaching and electrically interconnecting a semiconductor device (16) to the metallization pattern. A resin (18) is transfer molded about the semiconductor device, the electrical interconnections (17), and the metallization pattern so as to form an assembly, and a metal coating (19) is applied via vacuum deposition or plating to interconnect with a portion of the metallization pattern.
    Type: Grant
    Filed: February 4, 1991
    Date of Patent: September 17, 1996
    Assignee: Motorola, Inc.
    Inventors: Peter B. Gilmore, Kenneth R. Thompson
  • Patent number: 5555112
    Abstract: In a liquid crystal display substrate in which the pixel electrode is applied with a voltage through the drain and source of a thin-film transistor (TFT) that conducts by a voltage applied to the TFT gate electrode, this gate electrode and a busline connected to the gate electrode are formed as a multi-layered structure consisting of a gate layer and at least two layers of a gate insulation film and an amorphous silicon film. The multi-layered structure is formed by etching through a single mask.
    Type: Grant
    Filed: February 9, 1994
    Date of Patent: September 10, 1996
    Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.
    Inventors: Ryoji Oritsuki, Minoru Hiroshima, Masahiro Yanai, Masaaki Matsuda, Toshikazu Horii, Yuichi Hashimoto, Hayao Kozai, Kenkichi Suzuki, Masaru Takabatake, Takashi Isoda
  • Patent number: 5554867
    Abstract: A nonvolatile semiconductor memory device is provided including a DINOR (Divided Bit Line NOR) type cell that allows further reduction of the cell size while ensuring immunity from drain-disturb. In the nonvolatile semiconductor memory device, a sub-bit line is formed to have a length corresponding to the length of 16-1024 memory cell transistors. Memory cell transistors corresponding to the length of that sub-bit line are connected to the sub-bit line. Thus, the effective cell size is reduced while ensuring immunity from drain-disturb.
    Type: Grant
    Filed: December 9, 1994
    Date of Patent: September 10, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Natsuo Ajika, Atsushi Ohba
  • Patent number: 5552636
    Abstract: A discrete element electronic package (100) includes a heat spreader (180) with a cavity (185) for receiving a substrate (110), a substrate (110) mounted within the cavity (185) of the heat spreader (180), a heat-generating semiconductor device (170), such as a power transistor (170), mounted on the substrate (110), and electrical connectors (140) located on the substrate (110) to provide an electrical interface to the semiconductor device (170).
    Type: Grant
    Filed: November 28, 1994
    Date of Patent: September 3, 1996
    Assignee: Motorola, Inc.
    Inventor: Robert F. Darveaux
  • Patent number: 5550409
    Abstract: In order to obtain a semiconductor device having an internal wire of low resistance, a conductive layer whose surface is silicified is provided in a surface of a semiconductor substrate. A conductor whose surface is silicified is provided on the semiconductor substrate in proximity to the conductive layer. This semiconductor device is provided with an internal wiring layer, which is formed by a titanium film and a titanium silicide layer for electrically connecting the surface of the conductive layer and a surface of an end of the conductor with each other, to cover a side wall surface and a bottom surface of a contact hole.
    Type: Grant
    Filed: November 14, 1994
    Date of Patent: August 27, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takehisa Yamaguchi, Hidekazu Oda
  • Patent number: 5550553
    Abstract: A dielectric rod antenna including a dielectric rod, a ring-shaped conductive film provided on an outer peripheral surface of the dielectric rod, and a waveguide. The conductive film is provided on an outer peripheral surface portion of the dielectric rod which is inclined from a base end portion toward a forward end portion. The conductive film is arranged to intersect the waveguide so as to form a substantially V-shaped cross-sectional area.
    Type: Grant
    Filed: February 17, 1994
    Date of Patent: August 27, 1996
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Kazuhisa Yamaki, Kazunari Kawabata
  • Patent number: 5550630
    Abstract: A method for analyzing the structures of chemical organic compounds, polymers, polynucleotides and peptides is disclosed. The method uses the integrated intensity of spectral light absorption in wide or narrow regions of the ultraviolet and/or visible spectrum and relates these parameters additively to the structural characteristics of the analyzed chemical compound. For the analysis of polymers, nucleotides and/or peptides the integrated intensities of spectral absorption are used sequentially in narrow regions of the ultraviolet light which enables the determination of the molecular weight and the complete amino acid composition of the analyzed compound. All these procedures are interconnected in an automatic spectrophotometric structural analyzer.
    Type: Grant
    Filed: March 19, 1993
    Date of Patent: August 27, 1996
    Assignee: The United States of America as represented by the Secretary of Agriculture
    Inventor: Joseph Chrastil
  • Patent number: 5545913
    Abstract: An assembly facilitates mounting a set of abutted semiconductor chips, such as chips aligned to form a single full-page-width linear array of photosensors in a digital scanner or copier. An elongated bead of electrically conductive adhesive extends along a surface of a support substrate. A plurality of semiconductor chips is disposed along the elongated bead, each semiconductor chip including a linear array of photosensors on a front surface thereof, and a back surface attached to the support substrate by the electrically conductive adhesive. A connection block is disposed along another portion of the elongated bead, the block including a first surface contacting the bead, a second surface, and a conductor extending from the first surface to the second surface.
    Type: Grant
    Filed: October 17, 1994
    Date of Patent: August 13, 1996
    Assignee: Xerox Corporation
    Inventors: Kraig A. Quinn, Josef E. Jedlicka, Brian T. Ormond
  • Patent number: 5543648
    Abstract: A semiconductor member with a monocrystalline semiconductor layer for forming a functional element. The main plane of the monocrystalline semiconductor layer has a center line average surface roughness Ra of not more than 0.4 nm when the main plane is washed with an aqueous ammonia-hydrogen peroxide solution in a ratio of NH.sub.4 OH:H.sub.2 O.sub.2 :H.sub.2 O of 1:1:5 by volume at a washing temperature of 85.degree. C. for a washing time of 10 minutes.
    Type: Grant
    Filed: December 19, 1995
    Date of Patent: August 6, 1996
    Assignee: Canon Kabushiki Kaisha
    Inventor: Mamoru Miyawaki
  • Patent number: 5541449
    Abstract: A semiconductor die carrier may include an insulative substrate; an array of groups of multiple electrically conductive contacts arranged in rows and columns on the insulative substrate, wherein the groups from adjacent rows are staggered as are the groups from adjacent columns, and a portion of each group overlaps into an adjacent row or an adjacent column of the groups of the array; a semiconductor die; and structure for providing electrical connection between the semiconductor die and the conductive contacts.
    Type: Grant
    Filed: March 11, 1994
    Date of Patent: July 30, 1996
    Assignee: The Panda Project
    Inventors: Stanford W. Crane, Jr., Maria M. Portuondo
  • Patent number: 5541753
    Abstract: A liquid crystal display comprises a nematic liquid crystal layer disposed between alignment layers. The alignment layers are formed on substrates which also carry display control electrodes connected to a drive circuit. Polarisers are provided on opposite sides of the substrates. The alignment layers are arranged such that the liquid crystal molecule pretilt angles at the surfaces of the alignment layers are parallel. The liquid crystal layer has a retardance equal to (M+1).lambda./2 at a first operating voltage and M.lambda./2 at a second operating voltage, where M is an integer greater than zero or less than minus one and .lambda. is a wavelength of visible light.
    Type: Grant
    Filed: March 10, 1994
    Date of Patent: July 30, 1996
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Edward P. Raynes, Jonathan Harrold, Shuichi Kohzaki
  • Patent number: 5541447
    Abstract: A lead frame for use in producing of a semiconductor integrated circuit comprises a lead frame member, a plurality of leads, a tie bar, a plurality of auxiliary leads, a support-stay portion and a connecting portion. A semiconductor element such as an IC chip is mounted on a semiconductor-element-mounting portion of the lead frame member, while the leads are arranged along and extending from a side portion of the lead frame member. The tie bar is connected among the leads and auxiliary leads at their tip-edge portions. Herein, the auxiliary leads are electrically unconnected from the semiconductor element. Further, the support-stay portion is provided at a corner portion of the lead frame member. The connecting portion is provided between a base-edge portion of the support-stay portion and a base portion of the auxiliary lead. A location of the connecting portion is selected in such a manner than the connecting portion will be unaffected by bending of the leads.
    Type: Grant
    Filed: September 14, 1994
    Date of Patent: July 30, 1996
    Assignee: Yamaha Corporation
    Inventors: Yoshihisa Maejima, Seiya Nishimura, Masayoshi Takabayashi, Tokuyoshi Ohta
  • Patent number: 5541748
    Abstract: A liquid crystal display provided with a matrix of inverted-stagger thin-film transistors has a plurality of gate insulating films formed over gate lines and including one insulating film formed in contact with gate electrodes of the thin-film transistors and in self-alignment with gate lines in the picture display area of the liquid crystal display. The rest of the gate insulating films not crossing the gate electrodes and in contact with a semiconductor layer are patterned in conformity with drain electrodes (data lines), and a semiconductor layer and an insulating film not crossing the drain electrode and crossing the gate electrodes are patterned at the same time. The method has less steps than the conventional method, is capable of fabricating a liquid crystal display capable of displaying pictures in a high picture quality at a high yield rate.
    Type: Grant
    Filed: June 7, 1994
    Date of Patent: July 30, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Kikuo Ono, Junichi Ohwada, Hideaki Yamamoto, Hiroaki Asuma, Nobutake Konishi