Patents Examined by Rolf Hille
  • Patent number: 5528080
    Abstract: Conductive feed-throughs formed by partially migrating conductive material in a body of semiconductor material are used to provide electrical interconnections between the semiconductor surfaces. In addition, the conductive feed-throughs furnish mechanical support and thermal dissipation paths for the body of semiconductor material.
    Type: Grant
    Filed: December 13, 1994
    Date of Patent: June 18, 1996
    Inventor: Edward F. Goldstein
  • Patent number: 5528074
    Abstract: A semiconductor device includes a substrate having a microwave semiconductor element, a microwave transmission line disposed on the substrate and electrically connected to the microwave semiconductor element, and a waveguide terminal structure disposed in the substrate and connected to an end of an external waveguide, wherein an end of a signal conductor of the microwave transmission line is included in the waveguide terminal structure. Input and output of microwave signals between the semiconductor device and an external device are carried out simply by applying an end of the external waveguide to the waveguide terminal structure. As a result, even when the substrate of the semiconductor device warps, an input-output characteristic evaluation of the semiconductor device is carried out with high stability.
    Type: Grant
    Filed: January 26, 1995
    Date of Patent: June 18, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kei Goto, Takayuki Katoh
  • Patent number: 5528370
    Abstract: In a system for measuring variations in thickness of an optical etalon, a light source and a diffraction grating are mounted on a base structure with an axle. A lever arm is affixed to the axle, and a micrometer is held in contact with the lever arm. The grating directs a into an optical path a wavelength of radiation dependent on orientation of the grating. The etalon is supported in the optical path to effect a fringe pattern representing variations in thickness of in the etalon. The orientation is varied with the micrometer so as to vary the wavelength to the etalon and thereby positioning of the fringe pattern across the etalon which is viewed through a microscope. The micrometer measures the variation of orientation and thereby variation in thickness across the interference element.
    Type: Grant
    Filed: March 29, 1995
    Date of Patent: June 18, 1996
    Assignee: The Perkin-Elmer Corporation
    Inventors: David Tracy, Paul G. Saviano
  • Patent number: 5528051
    Abstract: The semiconductor component, comprises a succession of alternating stacked layers of a III-V semiconductor material with a large forbidden band such as Al.sub.x Ga.sub.1-x As and a III-V semiconductor material with a small forbidden band such as GaAs with p-doping, defining a quantum (9) with sub-bands of HH and LH type in the region of the layer comprising the material with a small forbidden band in the valence band diagram (E.sub.v) of each corresponding heterostructure. According to the invention, the thickness of the material with a small forbidden band is essentially selected in such a manner that only two quantum sub-levels LH.sub.1 and HH.sub.1 appear in the well, and the energy difference between these two sub-levels corresponds to the energy of the photons (6) to be detected, and the composition of the material with the large forbidden band is essentially selected in such a manner that the height adjacent the barrier (.DELTA.E.sub.
    Type: Grant
    Filed: July 22, 1994
    Date of Patent: June 18, 1996
    Assignee: Picogiga Societe Anonyme
    Inventor: Linh T. Nuyen
  • Patent number: 5526112
    Abstract: A probe for monitoring a fluid medium employing at least one fiber optic emitting a wave into the fluid medium. The fluid medium scatters or causes luminescence of the emitted wave which is then collected by at least one fiber optic. The probe includes a base having a hole and a window covering the hole of the base, wherein the window transmits electromagnetic waves. The probe collects scattered and luminescence of waves through one or more fiber optics placed behind the window and transmits the waves to a spectrometer connected to a computer which can analyze the fluid medium on a real-time on-line basis. Piezoresistive and temperature sensing elements are deposited on the window which can also serve as a force collector diaphragm. The elements are located primarily on the periphery of the diaphragm leaving a part of the diaphragm open for transmission and collection of the waves.
    Type: Grant
    Filed: March 5, 1993
    Date of Patent: June 11, 1996
    Inventor: Armen N. Sahagen
  • Patent number: 5523628
    Abstract: A method and apparatus for protecting metal bumped chips during processing and for providing mechanical support to interconnected chips. A protective adhesive stop is affixed to a metal bumped chip so that the height of the stop is at least as high as the metal bump. The stop protects the metal bump during routine handling. When the chip is interconnected to another bumped chip by cold welding their respective metal bumps, the stop contacts the face of the second chip and provides mechanical support. The stop is preferably a thermoplastic that is heated to adhere it to the second chip. The addition of the protective stop facilitates automated processing of metal bumped chips, and provides stronger, faster, and lower power chips.
    Type: Grant
    Filed: August 5, 1994
    Date of Patent: June 4, 1996
    Assignee: Hughes Aircraft Company
    Inventors: Ronald L. Williams, Joe B. Tyra
  • Patent number: 5523621
    Abstract: In order to set the potential of corner leads formed from a lead frame equal to that of power source leads such as ground, a multilayer wiring substrate is mounted on a mounting substrate of a package and its potential is set equal to that of the power source leads, or a multilayer mounting substrate is formed to electrically connect electrode pads of a semiconductor substrate to the power source and corner leads by bonding wires. The inductance of the power source leads can be lowered, and the number of signal leads interposed between the power source leads can be reduced to the minimum. Consequently, variations in frequency used in the entire package can be prevented, and impedance matching can be made.
    Type: Grant
    Filed: May 11, 1995
    Date of Patent: June 4, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Makoto Kikuchi
  • Patent number: 5523591
    Abstract: An assembly of an LED array of LED elements and lens array provides for improved flattening of the peaks and valleys of the light profile emitted by the array after lensing. The assembly employs the line spread function (LSF) of the lens to determine the positioning of opaque electrodes overlying each LED region. The electrodes then function not only as a means for current injection into the LED, but also to modulate light intensity across the width of the region to aid in properly shaping the LED light output profile to best fit the lens characteristics. The LSF of the lens may also be used to define areas in which to adjust the light-emitting layer or anti-reflection coating thicknesses in directions extending across the LED regions to accentuate or attenuate light output intensity.
    Type: Grant
    Filed: January 25, 1995
    Date of Patent: June 4, 1996
    Assignee: Eastman Kodak Company
    Inventors: Paul J. Fleming, Gopalan Rajeswaran, Yee S. Ng
  • Patent number: 5523625
    Abstract: A semiconductor integrated circuit device has upper wirings extending on an inter-level insulating layer covering a lower wiring at spacing with zig-zag side surfaces between the upper wirings, and the zig-zag lines are transferred to the inter-level insulating layer so as to prevent the upper wirings from short circuit due to a residue of conductive material for the upper wirings.
    Type: Grant
    Filed: October 19, 1994
    Date of Patent: June 4, 1996
    Assignee: NEC Corporation
    Inventor: Mituharu Hayashi
  • Patent number: 5523600
    Abstract: A compact MOS type active device is constructed at least partially in an opening in an insulation layer, such as an oxide layer, above a portion of a semiconductor substrate forming a first source/drain region of the MOS type active device. A semiconductor material, on the sidewall of the opening, and in electrical communication with the portion of the substrate forming the first source/drain region of the device, comprises the channel portion of the MOS device. A second source/drain region, in communication with an opposite end of the channel, is formed on the insulation layer adjacent the opening and in electrical communication with the channel material in the opening. A gate oxide layer is formed over the channel portion and at least partially in the opening, and a conductive gate electrode is then formed above the gate oxide.
    Type: Grant
    Filed: October 26, 1994
    Date of Patent: June 4, 1996
    Assignee: LSI Logic Corporation
    Inventor: Ashok K. Kapoor
  • Patent number: 5523601
    Abstract: A high-breakdown-voltage MOS transistor includes a substrate of one conductivity and a semiconductor layer of the other conductivity type, a drain electrode, a diffusion layer of one conductivity type, a base region of one conductivity type, a source region, a gate electrode, a source electrode, and a heavily doped layer. The diffusion layer and the substrate are electrically connected to the source region.
    Type: Grant
    Filed: December 9, 1994
    Date of Patent: June 4, 1996
    Assignee: NEC Corporation
    Inventor: Hiroshi Yanagigawa
  • Patent number: 5523602
    Abstract: Disclosed is an multi-layered SOI substrate, which includes a supporting substrate, and a first insulator, a semiconductor film, a second insulator and a single crystalline semiconductor film (SOI film) which are layered on the main surface of the supporting substrate. The SOI substrate is formed by a direct bonding technique, and a bipolar transistor and an MOS transistor are formed using the single crystalline semiconductor film (SOI layer). The extremely shallow junction can be formed without epitaxial growth, thereby significantly increasing the operation speed of the semiconductor device at a low cost.
    Type: Grant
    Filed: August 16, 1994
    Date of Patent: June 4, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Masatada Horiuchi, Takahiro Onai, Katsuyoshi Washio
  • Patent number: 5523609
    Abstract: A solid-state image sensing device, such as a charge-coupled image sensor, has a plurality of sensor regions arranged in two-dimensions with vertical transfer lines associated with respective vertical rows of the sensor regions for transfer of signal charges read from the sensor regions. Each vertical transfer line comprises a charge transfer region for transferring the signal charges read from the sensor regions. A gate electrode is formed on an insulating layer over the signal charge transfer regions, a light shielding layer is formed on an interlayer insulating layer over the gate electrode, and a buffer film containing hydrogen underlies the light shielding layer. The buffer layer, such as a buffer layer containing hydrogen, prevents damage attributable to film forming processes and the diffusion of impurities from the light shielding layer, and supplies hydrogen into the interface between the substrate and an oxide film to improve the condition of the interface. Thus, dark current can be reduced.
    Type: Grant
    Filed: December 23, 1994
    Date of Patent: June 4, 1996
    Assignee: Sony Corporation
    Inventor: Takashi Fukusho
  • Patent number: 5523872
    Abstract: A liquid crystal apparatus includes: (a) a liquid crystal panel having a longitudinal direction and containing therein a chiral smectic liquid crystal comprising plural layers of liquid crystal molecules aligned to have a common layer normal, each layer being composed of a plurality of liquid crystal molecules, each liquid crystal molecule being oriented to one of plural stable orientation states in the absence of an electric field; and (b) a panel supporting means comprising two fixing axes which extend in parallel with the longitudinal direction of the liquid crystal panel and fix the peripheral sides of the liquid crystal panel, the fixing axes forming an intersection angle .theta..sub.1 in the range of 0-25 degrees with the common layer normal.
    Type: Grant
    Filed: February 23, 1994
    Date of Patent: June 4, 1996
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yukio Hanyu, Masanobu Asaoka
  • Patent number: 5522452
    Abstract: In a liquid cooling system for a printed circuit board on which integrated circuit packages are mounted, heat sinks are secured respectively to the packages in heat transfer contact therewith. Nozzles are provided in positions corresponding to the heat sinks. A housing is tightly sealed to the printed circuit board to enclose the packages, heat sinks and nozzles in a cooling chamber. A feed pump pressurizes working liquid cooled by a heat exchanger and supplies the pressurized liquid to the nozzles for ejecting liquid droplets to the heat sinks. A liquid suction pump is connected to an outlet of the housing for draining liquid coolant to the heat exchanger and a vapor suction pump is connected to a second outlet of the housing for sucking vaporized coolant to the heat exchanger. The cooling chamber is maintained at a sub-atmospheric pressure to promote nucleate boiling of the working fluid.
    Type: Grant
    Filed: November 22, 1993
    Date of Patent: June 4, 1996
    Assignee: NEC Corporation
    Inventors: Tsukasa Mizuno, Hirokazu Miyazaki, Kazuhiko Umezawa
  • Patent number: 5521397
    Abstract: Layers each consisting of one of two types of compound semiconductors A and B different from each other in a lattice constant a and an energy band gap Eg (a(A)>a(B), Eg(A)<Eg(B)) are stacked in a [111] direction on a compound semiconductor substrate whose major surface is a surface. When each layer consisting of the compound semiconductor A serves as a well layer and each layer consisting of the compound semiconductor B serves as a barrier layer, the barrier layer is formed to have a thickness larger than the critical film thickness of strain relaxation in that barrier layer and is thereby so strained as to be pulled in a direction parallel to a crystal growth surface. The well layer is so strained as to be compressed in the direction parallel to the crystal growth surface owing to partial relaxation of a strain confined in the barrier layer. This can achieve as large an optical bistable effect as possible while maintaining the light blue-shift absorption characteristic.
    Type: Grant
    Filed: August 9, 1993
    Date of Patent: May 28, 1996
    Assignee: Olympus Optical Co., Ltd.
    Inventor: Xiong Zhang
  • Patent number: 5521439
    Abstract: A combination of an electronic semiconductor device comprising a metal plate and a plastics body which encapsulates the metal plate leaving at least a major surface thereof exposed, a heat sink, and means of fastening the heat sink to the device. To enable securement of the heat sink on the device without any external fastening arrangement having to be used, and without unduly straining the solder spot of the device pins to a printed circuit, the device is provided with undercut regions on opposite sides adjacent to the exposed surface of the plate for releasable engagement by the fastening means.
    Type: Grant
    Filed: April 5, 1994
    Date of Patent: May 28, 1996
    Assignee: SGS-Microelectronics S.r.l.
    Inventors: Paolo Casati, Giuseppe Marchisi
  • Patent number: 5521401
    Abstract: The invention may be incorporated into a method for forming a vertically oriented semiconductor device structure, and the semiconductor structure formed thereby, by forming a first transistor over a portion of a substrate wherein the first transistor has a gate electrode and a source and drain regions. First and second interconnect regions are formed over a portion of the gate electrode and a portion of the source and drain regions of the first transistor, respectively. A source and drain region of a second transistor is formed over the second interconnect. A Vcc conductive layer is formed over a portion of the source and drain region of the second transistor which is formed over the second interconnect.
    Type: Grant
    Filed: April 4, 1994
    Date of Patent: May 28, 1996
    Assignee: SGS-Thomson Microelectronics, Inc.
    Inventors: Mehdi Zamanian, James L. Worley
  • Patent number: 5521428
    Abstract: A flagless semiconductor device (10) includes a semiconductor die (22) having a plurality of bond pads (26) which are electrically coupled to a plurality of leads (16) by wire bonds (28). The die is supported by two cantilevered tie bars (18). Use of cantilevered tie bars decreases the total plastic-metal interface area in a plastic encapsulated device, thereby lessening the probability of internal delamination and package cracking. The cantilevered tie bars also permit a variety of die sizes to be used with the same lead frame design. Suitable configurations for cantilevered tie bars include, but are not limited to, U-shape, T-shape, and H-shape configurations.
    Type: Grant
    Filed: August 22, 1994
    Date of Patent: May 28, 1996
    Assignee: Motorola, Inc.
    Inventors: Tom R. Hollingsworth, Michael B. McShane
  • Patent number: 5521432
    Abstract: A semiconductor device includes a semiconductor chip, a die-pad on which the semiconductor chip is mounted, a package encapsulating the die pad and the semiconductor chip, and a plurality of leads electrically connected to the semiconductor chip and projecting from the package, wherein each of the leads has a lead body made of pure nickel (Ni) having a purity equal to or greater than 99% and a first film formed thereon, the first film being made of palladium (Pd).
    Type: Grant
    Filed: June 1, 1994
    Date of Patent: May 28, 1996
    Assignee: Fujitsu Limited
    Inventors: Kazuto Tsuji, Yoshiyuki Yoneda, Junichi Kasai, Michio Sono