Patents Examined by Rolf Hille
  • Patent number: 5520244
    Abstract: A cooling device formed in a thermally conductive substrate having a microstructure, such as a plurality of thermally conductive posts spaced apart by dimensions that induce capillary action in a liquid coolant. The posts extend away from the heated region and a space between the posts is supplied with liquid coolant which is contained by a meniscus near the tips of the posts. The coolant vaporizes at the meniscus and absorbs heat but, due to increased pressure in the coolant contained by the meniscus, does not boil within the space between the posts, allowing more liquid coolant contact with the thermally conductive substrate and posts. The vaporized coolant may be discharged into the air or into a chamber adjoining the tips having a lower pressure for removal of additional heat by gaseous expansion. The discharge of gaseous coolant allows the capillary flow of the liquid coolant in the space to be unimpeded, and the flow of liquid coolant may be augmented by a fluid pump.
    Type: Grant
    Filed: June 13, 1994
    Date of Patent: May 28, 1996
    Assignee: SDL, Inc.
    Inventors: David C. Mundinger, Donald R. Scifres
  • Patent number: 5521700
    Abstract: The present invention provides a lens meter capable of accurately measuring the optical characteristics of a lens including additive diopter and of providing highly reliable data representing the optical characteristics of the lens. The lens meter projects measuring light through a target mark on a lens, focuses an image of the target mark in a target image on a photo-detecting device, and determines the optical characteristics of the lens on the basis of a locus of the target image detected by the photo-detecting device.
    Type: Grant
    Filed: November 15, 1994
    Date of Patent: May 28, 1996
    Assignee: Nidek Co., Ltd.
    Inventors: Tadashi Kajino, Mikio Kurachi, Noritsugu Nozawa, Masanao Fujieda
  • Patent number: 5519251
    Abstract: A semiconductor device includes a semiconductor chip (11) having a top surface and a bottom surface, a plurality of leads (14) arranged under the bottom surface of the semiconductor chip (11), where the leads (14) have first ends (14a) electrically coupled to the semiconductor chip (11) and second ends which form external terminals (16) and each of the external terminals have a bottom surface, and a package (17, 31) encapsulating the semiconductor chip (11) and the leads (14) so that the bottom surface of each of the external terminals (16) is exposed at a bottom surface (17a, 31a) of the package (17, 31) and remaining portions of the leads (14) are embedded within the package (17, 31), where the package (17, 31) has a size which is approximately the same as that of the semiconductor chip (11) in a plan view viewed from above the top surface of the semiconductor chip (11).
    Type: Grant
    Filed: October 15, 1993
    Date of Patent: May 21, 1996
    Assignee: Fujitsu Limited
    Inventors: Mitsutaka Sato, Junichi Kasai
  • Patent number: 5519233
    Abstract: A microchip capacitor used as a circuit element in internal impedance matching circuits of microwave transistors is disclosed. A thin film resistor is used to make interconnection between two first metallized patterns in a paired electrode structure, and a pair of microstrip lines are used to make interconnection between the two first metallized patterns and the second metallized pattern. The thin film resistor and the microstrip lines form a Wilkinson type synthetic circuit wherein a signal flowing in the thin film resistor and a signal flowing in the microstrip lines cancel each other. An isolation between the first and second metallized patterns is improved.
    Type: Grant
    Filed: June 3, 1994
    Date of Patent: May 21, 1996
    Assignee: NEC Corporation
    Inventor: Tomoyoshi Fukasawa
  • Patent number: 5519231
    Abstract: In order to obtain a pressure-connection type semiconductor device while preventing misregistration of a semiconductor base substrate and a thermal compensator with no penetration of an insulating/holding material and a method suitable for fabricating this device, concentric first and second steps (31c, 31a) are provided on an upper major surface of a first thermal compensator (31) from its outer periphery toward the center. A corner groove (3b) is provided along the overall periphery of an inner comer of the first step (31c), in the form of a ring. Since no insulating/holding material is provided in a contact surface between the semiconductor the substrate and the thermal compensator, the semiconductor base substrate and the thermal compensator are maintained in excellent electrical contact while no local stress is applied to the semiconductor substrate when the same is brought into pressure contact with the thermal compensator.
    Type: Grant
    Filed: November 15, 1994
    Date of Patent: May 21, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Nobuhisa Nakashima, Tokumitsu Sakamoto, Yuzuru Konishi
  • Patent number: 5519492
    Abstract: An optical arrangement or length- or angle-measuring device comprising an illumination device for generating partial ray beams and an image lens to receive and transmit the partial ray beams, wherein each of the received partial ray beams defines an angle of inclination with respect to the image lens. The optical arrangement further comprises a plurality of detectors to receive the transmitted partial ray beams and the detectors are positioned so that the distance between the image lens and the individual photodetectors is a function of the angle of inclination of the partial ray beams received by the image lens.
    Type: Grant
    Filed: June 25, 1993
    Date of Patent: May 21, 1996
    Assignee: Dr. Johannes Heidenhain GmbH
    Inventors: Wolfgang Holzapfel, Walter Huber
  • Patent number: 5519252
    Abstract: In a power semiconductor device having a power circuit 1 and a control circuit 2 incorporated in a resin case 4, said circuits being mounted on different substrates 1a and 2a and interconnected internally, and power terminals 6 and control terminals 7 connected to the power and control circuits, respectively, being drawn out of the case, the power terminals 6, the control terminals 7 and lead pins 13 are preliminarily molded by an insert technique together with the case as the power terminals 6 and the control terminals 7 are arranged at the peripheral edge of the case 4 whereas the lead pins 13 for establishing interconnection between the power and control circuits are arranged on a pin block 12 provided at the middle stage within the case, and the substrate 1a for the power circuit is mounted on a heat dissipating metal base 11 combined with the bottom side of the case 4 and the substrate 2a for the control circuit on the pin block 12, with the power terminals, control terminals and the pin block being sold
    Type: Grant
    Filed: December 21, 1994
    Date of Patent: May 21, 1996
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Shin Soyano, Susumu Toba
  • Patent number: 5517053
    Abstract: A frequency stable oscillating device includes an oscillating transistor. A heating element is disposed in close proximity to the oscillating transistor. A temperature sensor is mounted in close proximity to the oscillating transistor. A temperature control device supplies a variable signal which is dependant upon a local temperature of the oscillating transistor, wherein the variable signal controls the operation of the heating element. The heating element may alternately consist of one or more resistive patches, or one or more heating transistors which are biased to provide sufficient heating. The oscillating device may be formed from either IC or MMIC technologies, and may be formed from either silicon or GaAs.
    Type: Grant
    Filed: January 9, 1995
    Date of Patent: May 14, 1996
    Assignee: Northrop Grumman Corporation
    Inventors: Gregory R. Dietz, Sanjay Moghe, Richard R. Becker
  • Patent number: 5517057
    Abstract: Methods of fabrication for electronic modules having electrically interconnected side and end surface metallization layers and associated electronic modules are set forth. The methods include providing a stack comprising a plurality of stacked IC chips. A side surface thin-film metallization layer is formed on the stack. Next, an end surface thin-film metallization layer is formed the stack such that the side surface and end surface thin-film metallization layers directly electrically interconnect. Alternatively, each IC chip of a stack may include an end surface metallization layer such that separate formation of an end surface metallization layer on an end surface of the stack is unnecessary. The methods also include forming an electronic module by first providing a long stack of IC chips, testing the chips of the stack, and then segmenting the long stack into multiple small stacks of functional IC chips based upon the test results.
    Type: Grant
    Filed: May 26, 1995
    Date of Patent: May 14, 1996
    Assignee: International Business Machines Corporation
    Inventors: Kenneth E. Beilstein, Jr., Claude L. Bertin, John E. Cronin, Wayne J. Howell, James M. Leas, Robert B. Phillips
  • Patent number: 5517303
    Abstract: A fiber optic interferometric sensor system utilizing a reference transducer and an optical source having a short coherence length in comparison to the optical transit time through the sensor. The optical source is used to interrogate a remotely located fiber optics sensor which has an optical path difference between two reflecting surfaces or between one reflecting surface and a beam transmitted through the sensor such that the optical beams are incoherent for the optical source used. The reflected and transmitted beams are then coupled to a reference transducer, located remotely from the sensor and preferably near the electronic processing circuitry. The reference transducer is designed with an optical path length difference to produce a coherent combination for the optical path length differences of both the sensor and the reference transducer thereby forming a highly sensitive interferometer.
    Type: Grant
    Filed: March 8, 1993
    Date of Patent: May 14, 1996
    Assignee: Dylor Corporation
    Inventors: James H. Cole, Daniel F. Mathus
  • Patent number: 5517051
    Abstract: A first silicon controlled rectifier structure (220) is provided for electrostatic discharge protection, comprising a lightly doped semiconductor layer (222) having a first conductivity type and a face. A lightly doped region (224) having a second conductivity type opposite the first conductivity type is formed in the semiconductor layer (222) at the face. A first heavily doped region (226) having the second conductivity type is formed laterally within the semiconductor layer (222) at the face and is electrically coupled to a first node (62). A second heavily doped region (230) having the second conductivity type is formed laterally within the lightly doped region (224) and is electrically coupled to a second node (58). A third heavily doped region (228) having the first conductivity type is formed laterally within the lightly doped region (224) to be interposed between the first and second heavily doped regions (226 and 230) and is electrically coupled to the second node (58).
    Type: Grant
    Filed: January 20, 1995
    Date of Patent: May 14, 1996
    Assignee: Texas Insturments Incorporated
    Inventor: Amitava Chatterjee
  • Patent number: 5514881
    Abstract: A semiconductor substrate for GaP type light emitting devices which includes an n-type single crystal substrate, an n-type GaP layer, and a p-type GaP layer formed on the n-type GaP single crystal substrate. The carbon concentration in the n-type GaP single crystal substrate is more than 1.0.times.10.sup.16 atoms/cc, but less than 1.0.times.10.sup.17 atoms/cc. The n-type GaP single crystal substrate is obtained from an n-type GaP single crystal grown by the Liquid Encapsulation Czochralski method wherein B.sub.2 O.sub.3 containing water corresponding to 200 ppm or more is used as an encapsulation liquid.
    Type: Grant
    Filed: January 23, 1995
    Date of Patent: May 7, 1996
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Munehisa Yanagisawa, Susumu Higuchi, Yu K. Tamura, Akio Nakamura, Toshio Otaki
  • Patent number: 5514909
    Abstract: Disclosed is an electrode for semiconductor devices capable of suppressing the generation of hillocks and reducing the resistivity, which is suitable for an active matrixed liquid crystal display and the like in which a thin film transistor is used; its fabrication method; and a sputtering target for forming the electrode film for semiconductor devices. The electrode for semiconductor devices is made of an Al alloy containing the one or more alloying elements selected from Fe, Co, Ni, Ru, Rh and Ir, in a total amount from 0.1 to 10 At %, or one or more alloying elements selected from rare earth elements, in a total amount from 0.05 to 15 at %.
    Type: Grant
    Filed: July 27, 1994
    Date of Patent: May 7, 1996
    Assignee: Kabushiki Kaisha Kobe Seiko Sho
    Inventors: Seigo Yamamoto, Katsutoshi Takagi, Eiji Iwamura, Kazuo Yoshikawa, Takashi Oonishi
  • Patent number: 5512778
    Abstract: A semiconductor device with an improved contact capable of improving junction breakdown voltage and junction leakage current by forming a contact at an active region without damaging bird' beak portions of its element-isolation oxide films and a method of making this semiconductor device. The semiconductor device comprises element-isolation oxide films formed on a semiconductor substrate, an etch barrier material film formed on bird's beak portions of element-isolation oxide films, an insulating film formed over the element-isolation oxide films and the etch barrier material layer, and a conductive material layer formed over the insulating film and in contact with the active region. In order to prevent the bird's beak portions of element-isolation oxide films from being damaged upon the formation of contact hole, the etch barrier material film has an etch selectivity different from that of a silicon oxide film formed on the active region.
    Type: Grant
    Filed: December 2, 1993
    Date of Patent: April 30, 1996
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: In S. Chung, Youn J. Kim
  • Patent number: 5512782
    Abstract: A semiconductor device for converting DC input power to AC output power includes a package having a rectangular shape with four side edges and containing a plurality of semiconductor chips therein. Two pairs of positive and negative terminals of DC input terminals are situated on the side edges to face to each other such that the same polar terminals in the positive and negative terminals face to each other. AC output terminals and control terminals are arranged on the side edges where the DC input terminals are not formed.
    Type: Grant
    Filed: October 4, 1994
    Date of Patent: April 30, 1996
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Shinichi Kobayashi
  • Patent number: 5513198
    Abstract: A package for a high power semiconductor laser comprising a hermetically sealed container filled with a dry gaseous medium containing oxygen. The presence of oxygen in the laser atmosphere is counter to standard practice in the art which teaches the use of an atmosphere of a dry inert gas. The package also includes a getter for organic impurities, e.g., a getter composed of a porous silica or a zeolite. The hydrogen content of the materials used to form the package are reduced by baking at an elevated temperature for an extended period of time, e.g., at 150.degree. C. for 200 hours.
    Type: Grant
    Filed: December 17, 1993
    Date of Patent: April 30, 1996
    Assignee: Corning Incorporated
    Inventor: Paul A. Jakobson
  • Patent number: 5512785
    Abstract: A semiconductor device (8) has an insulating layer (16) overlying a semiconductor substrate (12). The insulating layer has a first opening that defines an aperture (18) extending from the insulating layer to the semiconductor substrate, and at least a first portion of a first conductive terminal (42) is disposed in the aperture. A second conductive terminal (52) has a second portion (28) disposed in the aperture. The second portion of the second conductive terminal is separated from the first conductive terminal by a composite dielectric layer including a nitride layer (32) and an oxide layer (30). In one approach, the oxide layer is formed by the oxidation of the second portion of the second conductive terminal.
    Type: Grant
    Filed: November 30, 1994
    Date of Patent: April 30, 1996
    Assignee: Motorola, Inc.
    Inventors: Harrison B. Haver, Mark D. Griswold
  • Patent number: 5510895
    Abstract: A probe for monitoring a fluid medium employing at least one electromagnetic wave reflector and at least one fiber optic for analysis of the fluid medium. The probe includes a base having a hole, a window covering the hole of the base, wherein the window transmits electromagnetic waves and a electromagnetic reflector, spaced apart from the window, disposed to reflect at least part of the electromagnetic waves toward the window. The probe collects the reflected waves through one or more fiber optics placed behind a window to a fluid medium and transmits the waves to a spectrometer connected to a computer which analyzes the fluid medium on a real time on-line basis. Piezoresistive and temperature sensing elements are deposited on the window which also may function as a force collector diaphragm of thin refractory or a semiconductor materials. The piezoresistive elements are on the unsupported part of the diaphragm and at least part of the diaphragm is transparent to electromagnetic waves.
    Type: Grant
    Filed: March 5, 1993
    Date of Patent: April 23, 1996
    Inventor: Armen N. Sahagen
  • Patent number: 5510646
    Abstract: A metal-to-metal antifuse comprises a lower electrode comprising a first metal layer in an integrated circuit, a first barrier layer formed from a layer of TiW:N disposed over the lower electrode, a layer of antifuse material formed from amorphous silicon over the first barrier layer, a second barrier layer formed from a layer of TiW:N disposed over the layer of antifuse material, said second barrier layer, and an upper electrode over the second barrier layer, the upper electrode comprising a second metal layer in the integrated circuit.
    Type: Grant
    Filed: June 10, 1993
    Date of Patent: April 23, 1996
    Assignee: Actel Corporation
    Inventors: Abdul R. Forouhi, Iton Wang
  • Patent number: 5510653
    Abstract: Disclosed herein is a semiconductor device having a multilayer interconnection structure, which is provided with a plurality of via holes having constant diameters. Patterns of a first interconnection layer are provided on a semiconductor substrate. An interlayer insulating film is provided over the semiconductor substrate, to cover the patterns of the first interconnection layer. A silicon ladder resin film is applied onto the surface of the interlayer insulating film, to flatten the same. First and second via holes are provided through the silicon ladder resin film and the interlayer insulating film, to expose first and second coupling portions provided on the surfaces of the patterns of the first interconnection layer. A second interconnection layer is provided over the semiconductor substrate, to be connected with the first and second coupling portions through the first and second via holes respectively.
    Type: Grant
    Filed: March 31, 1993
    Date of Patent: April 23, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Noriaki Fujiki, Shigeru Harada, Hiroshi Adachi, Etsushi Adachi