Patents Examined by Rolf Hille
  • Patent number: 5541422
    Abstract: The invention relates to a tunnel diode provided with two metallically conducting electrodes (1, 2) with an insulating dielectric (3) in between, which forms a barrier with a barrier level for electrons and which has a thickness such that electrons can tunnel through the barrier from the one to the other electrode. Such a tunnel diode has the disadvantage that it has no memory. In many applications it is desirable for the tunnel diode to hold a certain switching state, such as open/closed. According to the invention, the tunnel diode is characterized in that the dielectric (3) comprises a layer of a material which is ferroelectric at room temperature with a remanent polarization which influences the barrier level. It is achieved thereby that the tunnel diode has various switching states in dependence on the remanent polarization of the dielectric (3). The switching state is maintained until the polarization of the dielectric (3) changes.
    Type: Grant
    Filed: December 12, 1994
    Date of Patent: July 30, 1996
    Assignee: U.S. Philips Corporation
    Inventors: Ronald M. Wolf, Paulus W. M. Blom, Marcellinus P. C. M. Krijn
  • Patent number: 5539253
    Abstract: A resin-sealed semiconductor device includes a heat sink on which a semiconductor chip is provided. An output terminal is connected to the semiconductor chip. A casing surrounds the chip and part of the output terminal. The inside of the casing is filled with a sealing resin containing an aggregate such as glass particle. The chip is mounted in the area of an upper surface of the heat sink and the remaining area is covered with an epoxy resin film, which is from 10 .mu.m to 20 .mu.m thick. The resin film increases the bonding strength between the sealing resin and the heat sink and prevents the sealing resin from peeling away from the heat sink upon heat cycles due to different expansion coefficients.
    Type: Grant
    Filed: September 20, 1994
    Date of Patent: July 23, 1996
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Fumio Nagaune
  • Patent number: 5539214
    Abstract: A quantum bridge structure including wires of a semiconductor material such as silicon which are formed by selectively etching a superlattice of alternating layers of at least two semiconductor materials. The quantum bridge is useful as a photo emission device, a photo detector device, and a chemical sensor. The wires exhibit improved electrical conduction properties due to decreased Coulomb scattering.
    Type: Grant
    Filed: February 6, 1995
    Date of Patent: July 23, 1996
    Assignee: Regents of the University of California
    Inventors: William T. Lynch, Kang L. Wang, Martin O. Tanner
  • Patent number: 5539250
    Abstract: A plastic-molded-type semiconductor device is provided wherein two semiconductor chips, having main surfaces on which electrodes and circuits are formed, are arranged to face each other. A lead frame is placed between these two semiconductor chips and electrically connected to their electrodes, and a plastic package is formed by plastic-sealing the above components. To provide for secure and convenient electrical connections between the electrodes on the semiconductor chips and the lead frame, wiring patterns are provided on the main surfaces of the semiconductor chips through the intermediation of insulating films. With this structure, it is possible for two large-sized semiconductor chips having electrodes in their middle sections to be encased in a single, relatively thin package.
    Type: Grant
    Filed: June 11, 1991
    Date of Patent: July 23, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Makoto Kitano, Asao Nishimura, Akihiro Yaguchi, Ryuji Kohno, Nae Yoneda
  • Patent number: 5539246
    Abstract: A microelectronic integrated circuit includes a semiconductor substrate, and a plurality of microelectronic devices formed on the substrate. Each device has a periphery defined by a hexagon, and includes an active area formed within the periphery, a central terminal formed in a central portion of the active area, and interconnected first to third terminals formed in the active area adjacent to edges of the hexagon that are separated by other edges. First to third gates are formed between the first to third terminals respectively and the central terminal, and have contacts formed outside the active area adjacent to the other edges of the hexagon. The power supply connections to the central terminal and the first to third terminals, the conductivity type (NMOS or PMOS), and the addition of a pull-up or a pull-down resistor is selected for each device to provide a desired OR, NOR, AND or NAND function. The devices are interconnected using three direction routing based on hexagonal geometry.
    Type: Grant
    Filed: March 1, 1995
    Date of Patent: July 23, 1996
    Assignee: LSI Logic Corporation
    Inventor: Ashok Kapoor
  • Patent number: 5536968
    Abstract: A programmable read only memory (PROM) including an array of polysilicon fuse elements. The fuse array is formed within a semiconductor substrate including first and second patterned signal layers electrically insulated from one another. Each polysilicon fuse element within the array connects a first electrical conductor residing in the first patterned signal layer with a second electrical conductor residing in the second patterned signal layer. The polysilicon fuse element is in the form of a narrow strip and is folded in order to cause a current flowing through the clement to crowd, lowering the amount of current required to heat the fuse element to its melting point, i.e. the threshold current. The PROM is programmed by passing a threshold current through selected fuse elements.
    Type: Grant
    Filed: August 16, 1994
    Date of Patent: July 16, 1996
    Assignees: AT&T Global Information Solutions Company, Hyundai Electronics America, Symbios Logic Inc.
    Inventors: Harold S. Crafts, William W. McKinley, Mark O. Scaggs
  • Patent number: 5536952
    Abstract: This transistor is a pnp transistor having a heterojunction of p-type diamond (or BP.sub.x N.sub.1-x, 6HSiC) and n-type SiC (3CSiC)and having a structure in which a p.sup.+ -SiC (3CSiC ) layer, a p-SiC (3CSiC) layer, an n.sup.+ -SiC (3CSiC) layer, a p-diamond (or BP.sub.x N.sub.1-x, 6HSiC ) layer, and a p.sup.+ -diamond (or BP.sub.x N.sub.1-x, 6HSiC) layer are formed on a substrate, and a collector electrode, a base electrode, and an emitter electrode are formed on and electrically connected to the p.sup.+ -Sic layer, the n.sup.+ -SiC layer, and the layer, respectively. This semiconductor device has a high resistance to environment.
    Type: Grant
    Filed: July 26, 1994
    Date of Patent: July 16, 1996
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Shinichi Shikata
  • Patent number: 5536974
    Abstract: A semiconductor device having a high packaging yield is disclosed. A light directed to a light reflection area (20) formed on a packaging substrate (10) is reflected with an accurate angle. A light directed to a second light reflection area (50) formed on a semiconductor chip (40) is also reflected with an accurate angle. A relative inclination between the packaging substrate (10) and the semiconductor chip (40) is measured based on the reflection angles of the reflected lights.
    Type: Grant
    Filed: May 21, 1993
    Date of Patent: July 16, 1996
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Masanori Nishiguchi
  • Patent number: 5537242
    Abstract: Low-cost, thin-layer liquid crystal (LC) millimeter wave (MMW) phase modulators and phased array antennae are provided based on several types of open transmission strip-line, parallel-line, and ridge-guide configurations in which surface-aligned LCs are modulated reversibly with small applied electrical fields. Incorporated properly in the open transmission lines, the LC layer can modulate the propagating MMW with nearly its full value of birefringence. The modulator comprises: (a) at least one transmission line supported on a first substrate; (b) a dielectric medium comprising a liquid crystal or a liquid crystal composite and contacting the substrate and the transmission line(s), the liquid crystal or a liquid crystal composite (e.g.
    Type: Grant
    Filed: February 10, 1994
    Date of Patent: July 16, 1996
    Assignee: Hughes Aircraft Company
    Inventor: Khoon-Cheng Lim
  • Patent number: 5534725
    Abstract: A resin molded CCD package and a method for preparing the CCD package by employing a transfer molding using a low-priced plastic material having a good moldability. This package comprises a semiconductor chip as a CCD, a lead frame being integrally provided with a paddle and a plurality of leads, a film wall being attached to an upper surface of the semiconductor chip such that it surrounds a light reception region of the semiconductor chip, a glass lid for sealing the light reception region and transmitting an outside light to the region, a plurality of metal wires for electrically connecting a plurality of bond pads of the semiconductor chip to individual inner leads of the lead frame, and a mold resin package body for hermetically sealing a predetermined part including the semiconductor chip and the inner leads, both being wire-bonded to each other.
    Type: Grant
    Filed: November 7, 1994
    Date of Patent: July 9, 1996
    Assignee: Goldstar Electron Co., Ltd.
    Inventor: Ki R. Hur
  • Patent number: 5534999
    Abstract: Sub-micron particles in fluid such as ultrapure water are detected or monitored by a simple apparatus in which a light beam from a coherent light source (1) is converged (2) in such a manner that the light beam is focussed in a stream (3) of particle-containing fluid, the light passed through the stream and diffracted by the particles is received by a photo-detector (4) which is positioned at an opposite side of the coherent light source with respect to the stream and substantially on an optical axis of the light beam, so that the number of particles in the stream is counted from electrical signals emitted by the photo-detector.
    Type: Grant
    Filed: February 1, 1995
    Date of Patent: July 9, 1996
    Assignee: Shinmikuni Kikai Ltd.
    Inventors: Hiroshi Koshizuka, Takashi Kanatake
  • Patent number: 5534721
    Abstract: A lateral semiconductor device is disclosed having a semiconductor body of a first conductivity type, and a drift region having a second conductivity type opposite that of the first conductivity type and formed on a surface of the semiconductor body. A drain region formed in the drift region includes an end portion having a surface area including a predetermined surface radius of curvature and a first surface width; a transitional portion tapers from the first surface width to a second surface width; and a medial portion having the second surface width. A source region is formed in the drift region and spaced from the drain region.
    Type: Grant
    Filed: November 30, 1994
    Date of Patent: July 9, 1996
    Assignee: AT&T Corp.
    Inventor: Muhammed A. Shibib
  • Patent number: 5534727
    Abstract: A semiconductor device including an insulating film substrate having a surface, a high frequency semiconductor chip disposed on the surface, and circuit elements disposed on the surface and connected to the semiconductor chip wherein the insulating film substrate is bent into a U-shape, laminated, and encapsulated with a resin. The package of the device is miniaturized.
    Type: Grant
    Filed: September 23, 1994
    Date of Patent: July 9, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Akira Inoue
  • Patent number: 5534718
    Abstract: An improved light emitting diode (LED) package structure for an LED lighting device comprises a reflector having a bowl-shaped reflecting surface formed by a pressing technique. A stand member extends from the center of the reflecting surface to the focus point of the reflector to support an LED die thereon. This arrangement allows the reflecting surface to extend toward the center thereof in order to increase the reflecting surface area and thus increasing the luminance of the LED display.
    Type: Grant
    Filed: November 22, 1994
    Date of Patent: July 9, 1996
    Assignee: Hsi-Huang LIN
    Inventor: Fa-Sheng Chang
  • Patent number: 5532851
    Abstract: An optical switching element having a variable optical path length layer whose optical path length is varied and whose refractive index anisotropy is controlled by application of an external field; external field application device for applying the external field to the variable optical path length layer; a first non-varying optical path length layer formed at at least one surface of surfaces of the variable optical path length layer in a direction of thickness thereof, and having a refractive index which is greater than a maximum refractive index of the variable optical path length layer; and a second non-varying optical path length layer formed at at least one surface of the surfaces of the variable optical path length layer in the direction of thickness thereof, and having a refractive index which is less than a minimum refractive index of the variable optical path length layer. By controlling refractive index anisotropy of the variable optical path length layer, natural light can be modulated.
    Type: Grant
    Filed: April 8, 1994
    Date of Patent: July 2, 1996
    Assignee: Fuji Photo Film Co., Ltd.
    Inventor: Yoshihisa Usami
  • Patent number: 5532516
    Abstract: Via filling is enhanced by the techniques of 1) providing pillars immediately underneath semiconductor features, such as metal layer contacts (inter-connection points), and 2) polishing off excess via-filling material so that the via-filling plug is flush with the topmost insulating layer. The pillars are provided under every feature over which a via will be formed, so that an insulating layer surrounding the via will be thinner at the location of the feature. If necessary, polishing is continued to thin the insulating layer so that the plugs in initially selectively under-filled vias are made flush with the insulating layer. Method and apparatus are disclosed.
    Type: Grant
    Filed: March 28, 1995
    Date of Patent: July 2, 1996
    Assignee: LSI Logic Corportion
    Inventors: Nicholas F. Pasch, Roger Patrick
  • Patent number: 5530295
    Abstract: A heat sink incorporated into an electronic package. The package contains an integrated circuit enclosed by a dielectric housing. Coupled to the circuit is a lead frame which has a plurality of leads that extend from the outer edges of the housing. The heat sink has a bottom surface pressed against the lead frame and an opposite top surface that is exposed to the ambient. The heat sink also has a pair of oblique steps which engage the housing and insure that the sink does not become detached from the package.
    Type: Grant
    Filed: May 26, 1995
    Date of Patent: June 25, 1996
    Assignee: Intel Corporation
    Inventor: Behrooz Mehr
  • Patent number: 5530269
    Abstract: A light emitting device that comprises an organic LED array containing a plurality of light emitting pixels, the pixels each being located on a common electrically insulative transparent substrate, is characterized in that the transparent support is ultra thin, having a thickness less than the pitch of the pixels. The pixels in the LED array can be arranged in intersecting columns and rows, or they can comprise a line array.
    Type: Grant
    Filed: March 28, 1995
    Date of Patent: June 25, 1996
    Assignee: Eastman Kodak Company
    Inventor: Ching W. Tang
  • Patent number: 5530284
    Abstract: A semiconductor leadframe structure (11,41) includes a die bond portion (12) and a plurality of leads (13) coupled to the die bond portion (12). The leadframe structure (11) comprises a metal (23) such as copper or a copper alloy. At least one lead (28,29) includes a bond post (31) that has a major surface (32) for forming a wire bond. The major surface (32) includes an exposed area (33) of leadframe metal (23) and a covered area (34) of another metal (24) deposited onto the leadframe metal (23).
    Type: Grant
    Filed: March 6, 1995
    Date of Patent: June 25, 1996
    Assignee: Motorola, Inc.
    Inventor: Keith W. Bailey
  • Patent number: 5528061
    Abstract: A semiconductor integrated circuit device comprises a complementary inverter implemented by a series combination of a p-channel enhancement type switching transistor and an n-channel enhancement type switching transistor, and a multi-level wiring structure coupled between the drain nodes of the two switching transistors and a capacitive load, wherein the multi-level wiring structure comprises a lower level wiring strip coupled at both ends thereof with the drain nodes through two sets of contact holes, and an upper level wiring strip coupled at both ends thereof with the lower level wiring strip through two contact holes so that both charge and discharge currents bi-directionally flow the upper and lower wiring strips, thereby enhancing the resistance against electro-migration.
    Type: Grant
    Filed: October 11, 1994
    Date of Patent: June 18, 1996
    Assignee: NEC Corporation
    Inventor: Tadashi Iwasaki