Abstract: A method consists of the steps of depositing a Ti--Pt metal film on a SiN layer insulation film mounted on GaAs substrate, etching the Ti--Pt metal film to form a first metal layer, depositing a SrTiO.sub.3 insulating film, etching the SrTiO.sub.3 insulating film to form an insulating film, depositing a WSiN metal film according to a sputtering technique while controlling a deposition pressure of nitrogenous gas, etching the WSiN metal film to simultaneously form a second metal layer on the insulating film and a thin metal film resistive element on the SiN layer insulation film, depositing a SiO.sub.2 passivation film, and making via holes. SrTiO.sub.3 has a high relative dielectric constant, and WSiN has a high melting point. Nitrogen atoms in WSiN prevent oxygen atoms in the insulating film from diffusing into the second metal layer. The adhesion of second metal film to the insulating film is tight because of the sputtering technique.

Abstract: A system for measuring the tensile strength of a planar interface between a substrate and a coating which includes an energy source that generates an electromagnetic beam along a first axis, and a sample assembly disposed along the first axis having a first face, and a second face, where the first and second faces are oppositely opposed. The sample assembly includes a confining plate, an energy absorbing layer, a substrate and a coating having a free surface, all in intimate facing contact with each other, and where the sample and coating are in intimate facing contact forms a substrate/coating interface. The coating is positioned along the first axis so that the coating free surface forms the sample assembly second face and the confining plate forms the sample assembly first face. The sample assembly further includes a pulse element for generating a stress pulse responsive to the electromagnetic beam.

Abstract: A process for measuring overlay misregistration during semiconductor wafer fabrication including the use of an interferometric microscope in combination with a camera, a wafer transport stage, and data processing electronics to form an inspection system which can utilize either broadband or narrowband light, and large or small numerical aperture (NA) to develop a series of interference images taken at different Z (vertical) planes relative to the surface under investigation or P (pathlength) positions relative to interferometer arm difference. The data in these planes is then used to calculate the magnitude and phase of the mutual coherence between the object wave and the reference wave for each pixel in the image planes, and synthetic images are formed, the brightness of which is proportional to either the complex magnitude (the Magnitude Contrast Image or MCI) or the phase of the mutual coherence as the optical pathlength (the Phase Contrast Image or PCI) is varied.

Abstract: A miniaturized electronic device and a manufacturing method for the same is disclosed. Solder is provided on pads provided on leads and corresponding pads provided on an electronic part chip of the electronic device are placed on the solder. The solder is radiated with infrared rays and thereby melted. Then connecting parts are completed. This electronic device does not have a die and wires for bonding. Therefore, it is more miniaturized than a conventional electronic device.

Abstract: A high breakdown voltage semiconductor device includes a semiconductor substrate, an insulating layer formed on the semiconductor substrate, an active layer formed on the insulating layer and made of a high resistance semiconductor of a first conductivity type, a first impurity region of the first conductivity type formed in the active layer, and a second impurity region of a second conductivity type formed in the active layer and spaced apart from the first impurity region by a predetermined distance. The first impurity region is formed of diffusion layers. The diffusion layers are superimposed one upon another and differ in diffusion depth or diffusion window width, or both.

Abstract: A spectroanalytical system with radiation dispersing apparatus for dispersing radiation into a spectrum for concurrent application to an array of exit ports; sample excitation apparatus for exciting sample material to be analyzed to spectroemissive levels for generating a beam of radiation for dispersion by the dispersing structure; the exit port array including a corresponding array of detectors including a first detector positioned adjacent a first exit port positioned to sense first order radiation from an element of interest and a second detector positioned adjacent a second exit port to sense second order radiation from the same element of interest; and processing apparatus for responding to outputs of the first and second detectors to provide a compensated output as a function of the quantity of the element of interest in the sample material.

Abstract: A power transistor has a plurality of small emitter-base complexes arranged in an array. These complexes are electrically insulated from the surrounding semiconductor material by separating regions such that for the current supply to the collectors, a joint subcollector layer and thereupon a collector metallization exist outside of the emitter-base complexes and reaching up to the separating regions. The individual emitter-base complexes are electrically connected with each other via strip-shaped base supply lines and strip-shaped emitter supply lines, and also with a base contact surface and an emitter contact surface.

Abstract: A surface mount semiconductor package having a novel lead configuration which facilitates a higher packing density than presently available semiconductor packages. More particularly, the package includes a plurality of electrical leads each having a laterally outwardly extending portion, a downwardly extending portion depending from an inner distal end of the laterally extending portion, and a foot portion extending laterally inwardly from a lower distal end of the downwardly extending portion. A semiconductor chip is mounted, preferably by adhesive means such as insulating tape, to the foot portion of the leads. A plurality of electrical wires are connected between an upper surface of the chip and the laterally outwardly extending portion of respective ones of the leads. A protective body, such as a molded resin body, encapsulates the chip, the wires, the laterally outwardly and downwardly extending portions of the leads.

Abstract: Disclosed is a heat-resistant ohmic contact formed on a semiconducting diamond. It has a contact Ti layer having a thickness of 10 to 70 .ANG. and a carbide layer generated by the reaction between the Ti layer and the semiconducting diamond layer. A diffusion prevention layer composed of at least one kind material selected from a group consisting of refractory metals including W, Mo, Au, Pt and Ta, refractory alloys including Ti-W, and refractory compounds including TiC and TiN is formed on the contact Ti layer. With this construction, the diffusion and the oxidation of Ti can be prevented.

Abstract: A device isolation area structure in a semiconductor device is composed of two layers of a first device isolation film formed by selectively oxidizing a surface of a silicon substrate, and a second device isolation region formed in a single crystal silicon film covering the first device isolation film. A guard band region may be formed within the semiconductor substrate and immediately below the first device isolation film so as to be in contact with the first device isolation film. The device isolation area structure is suitable to high integration of the semiconductor device and provides less possibilities of occurrence of crystal defects.

Abstract: A semiconductor device includes a semiconductor substrate, impurity diffusion layers formed in the surface portions of the semiconductor substrate with a desired gap therebetween, an insulator layer bridged between the impurity diffusion layers on the semiconductor substrate and an electrode stacked on the insulator layer. The insulator layer is formed of a ferroelectric of IV-VI compound.

Abstract: A cooling structure for an integrated circuit that uses a liquid coolant to absorb heat directly from the integrated circuit includes a wiring substrate, an integrated circuit mounted on the wiring substrate, and a hollow cooling block, in which liquid coolant accumulates, disposed on a heat radiating surface of the integrated circuit. The upper portion of the cooling block is provided with an inlet port and an outlet port to allow the liquid coolant to enter and exit, respectively. A nozzle is mounted on the inlet port to jet the liquid coolant to the heat radiating surface. The lower portion of the cooling block consists of an opening portion which is opposed to the heat radiating surface, and which allows the liquid coolant to come in contact with and directly cool the heat radiating surface. The opening portion is liquid-tightly sealed to the heat radiating surface by a sealing member and/or a frame mounted on the heat radiating surface.

Abstract: A programmable semiconductor contact structure and method are provided. A semiconductor substrate has a first patterned conductive layer for forming an interconnect. A first insulating layer overlies the first patterned conductive layer. An opening is formed through the insulating layer to the first patterned conductive layer to form the contact via. A buffer layer overlies portions of the first insulating layer and covers the opening. A second conductive layer overlies the buffer layer. A third conductive layer then overlies the integrated circuit. The buffer layer is a material, such as amorphous silicon, which functions as an anti-fuse and can be programmed by application of a relatively high programming voltage.

Abstract: A pair of electrodes 3 are first formed on a substrate. Subsequently, an undoped diamond film is selectively deposited between the above electrodes. A B-doped diamond film is then selectively formed on both the insulating diamond film and part of each electrode. The substrate may be contained in a container provided with an opening portion from which only the B-doped diamond film is exposed.

Abstract: A semiconductor device having a substrate, a conductive layer formed on the substrate, an upper insulting film formed on the upper surface of the conductive layer and having a sectional shape with its width reduced upwardly, and a sidewall insulating film formed on the sidewall of the conductive layer and the upper insulating film having a sectional shape with its width reduced upwardly. The shape of the upper insulating film and, particularly, the sidewall insulating film prevent a polycrystalline silicon film formed on the upper insulating film and the sidewall insulating film from having a surface in the vertical direction relative to the substrate. Consequently, the disconnection of an upper layer interconnection can be effectively prevented, and miniaturization of elements can be achieved without forming fence-shaped residue when a conductive layer formed on the sidewall insulating film is anisotropically etched by plasma etching.

Abstract: A MOSFET device for ULSI circuits includes a semiconductor body having first and second spaced doped regions of a first conductivity type which function as source and drain regions, a third doped region between the first and second regions of a second conductivity type, and a first intrinsic region between the third doped region and the drain region, a channel of said MOSFET device including the third doped region and said first intrinsic region. Preferably the device further includes a second intrinsic region between the third doped region and the source region, the channel region of the MOSFET device including the third doped region, the first intrinsic region, and the second intrinsic region. The device further includes an insulating layer over the channel region and a gate electrode formed on the insulating layer over the channel region. A source electrode contact, the first doped region, and a drain electrode contact the second doped region. Several processes are described for fabricating the device.

Abstract: An ohmic contact to a III-V semiconductor material is fabricated. First, a III-V semiconductor material is provided. Source/drain regions are then formed in the III-V semiconductor material. On the III-V semiconductor material, a contact system is formed which is dry etchable using reactive ions such as chlorine or fluorine and substantially free of arsenic. Subsequently, a portion of the contact system is dry etched using reactive ions such as chlorine or fluorine to leave a portion of the contact system remaining on the source/drain regions. Then, the III-V semiconductor material and the contact system are annealed in an atmosphere substantially free of arsenic at a temperature at which at least a part of the contact system is alloyed with the source/drain regions to form an ohmic contact with the source/drain regions of the III-V semiconductor material.

Abstract: A semiconductor device has a conductive interconnection layer formed on a semiconductor substrate covered with a protection insulation film. A pad electrode opening is provided in the protection insulation film so that the surface of the conductive interconnection layer is exposed in the region which becomes the pad electrode. The conductive interconnection layer is electrically connected to an external terminal by a bonding wire. At least the surface of the protection insulation film in the proximity of the pad electrode opening and the inner peripheral side face of the pad electrode opening are covered with an elastic insulation film. The pad electrode opening is covered with the bonding wire. Since the conductive interconnection layer is not exposed at the pad electrode opening according to this structure, the phenomenon of moisture intruding into the pad electrode opening to corrode the conductive interconnection layer is prevented to improve reliability.

Abstract: The laser positioning device (10) as a housing (12) and a number of individual diode lasers (18) accommodated in the housing. The diode lasers can be energized to produce individual laser beams. Beam fanning means, preferably in the form of tubular lenses (28), are used to fan the laser beams to produce parallel, fanned beams (65) which are then projected from the housing (12) through a window (58). The positions of at least some of the diode lasers in the housing are adjustable by means of an endless cable and pulley mechanisms.

Abstract: In a multi-layer wiring structure of an integrated circuit device, occurrence of voids due to electromigration in the vicinity of an interface between upper and lower wiring layers is suppressed. The interface is cleaned in vacuum and grain size of the wiring layers is controlled. After an interlayer insulating film (16) having a connection hole (16A) is formed to cover a first wiring layer (14) of Al or an Al alloy, a second wiring layer (18) of Al or an Al alloy is formed and connected to the first wiring layer through the connection hole. When the second wiring layer is formed, grains (G.sub.2) of the second wiring layer are formed so as to be :respectively continuously adjacent to and substantially equal in size to grains (G.sub.1) of the first wiring layer which appear at the interface.