Patents Examined by Rolf Hille
  • Patent number: 5497031
    Abstract: A semiconductor chip is mounted on a chip-mounting section. A conduction path forming section having a plurality of conduction paths formed therein is placed around the chip-mounting section. A heat sinking board is bonded to the backsides of the chip-mounting section and the conduction path forming section. In the conduction path forming section, a second insulating layer is formed with notches, whereby the exposed area of conduction paths that are wire-bonded to the chip-mounting section is increased.
    Type: Grant
    Filed: September 22, 1994
    Date of Patent: March 5, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroyuki Kozono
  • Patent number: 5495889
    Abstract: A cooling device for power electrical components which have electrodes includes a heatsink including a circuit in which a cooling fluid can flow and having a first side for exchange of heat with the component to be cooled. An electrically insulative and good heat conductor material plate is disposed between the first side of the heatsink and a first side of an electrical connection. A second side of this electrical connection makes thermal and electrical contact with one electrode of a component. The heatsink and the electrical connection are mechanically joined so that the device forms a compact assembly.
    Type: Grant
    Filed: February 9, 1994
    Date of Patent: March 5, 1996
    Assignee: GEC Alsthom Transport SA
    Inventor: Jean-Luc Dubelloy
  • Patent number: 5495114
    Abstract: A miniaturized electronic imaging chip has stratified layers wherein a base silicon layer has a peripheral edge defining an area and a thickness which allows passage therethrough of most UV, visible and IR light. A pixel layer is formed on the back side of this first silicon layer. At least one interconnect layer is bonded to the pixel layer. Electric leads are bump bonded to the bonding pads on the outermost interconnect layer and extend away from it within the area for attachment to means for sensing electrical signals generated by an image projected onto the pixel layer through the silicon layer. Preferably, the leads are perpendicular to the chip.
    Type: Grant
    Filed: November 22, 1993
    Date of Patent: February 27, 1996
    Inventor: Edwin L. Adair
  • Patent number: 5495126
    Abstract: A polycrystalline diamond is prepared by chemical vapor deposition (step 101). A surface of the polycrystalline diamond is metallized (step 102). The metallized surface of the polycrystalline diamond is grooved with a YAG laser (step 103). A wedge or the like is driven into the grooves of the polycrystalline diamond to pressurize the same, whereby the polycrystalline diamond is divided along the grooves (step 104). Alternatively, a surface of a polycrystalline diamond prepared by chemical vapor deposition is grooved with a YAG laser (step 112), and the surface of the polycrystalline diamond is metallized (step 113) after the grooving. The obtained diamond heat sink (10) includes a first layer (11a) grooved with a laser, and a mechanically divided second layer (11b). Graphite adheres to the outer peripheral surface of the first layer (11a). The outer peripheral surface of the second layer (11b) has a greater surface roughness than that of the first layer (11a).
    Type: Grant
    Filed: January 14, 1994
    Date of Patent: February 27, 1996
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takahisa Iguchi, Tsutomu Nakamura, Tetsuo Nakai
  • Patent number: 5493150
    Abstract: An IC carrier comprising a case for receiving an IC, a carrier body for receiving the case, and a positioning device for correctly positioning the IC which is received in the case.
    Type: Grant
    Filed: February 14, 1994
    Date of Patent: February 20, 1996
    Assignee: Yamaichi Electronics Co., Ltd.
    Inventors: Noriyuki Matsuoka, Kazumi Uratsuji, Shunji Abe
  • Patent number: 5493404
    Abstract: Method and apparatus for sensing the color of articles wherein a first pair of wavelengths is selected on a plurality of light reflection curves in terms of reflected light wavelength spectrum, these curves being associated with a plurality of articles constituting a sample representative of the color range to be sensed. The first pair of wavelengths delimits a first range of wavelengths corresponding to light reflection values in these curves, the light reflection values in each of the curves being in a substantially linear relationship over said first range of wavelengths. Each article to be inspected is illuminated with light comprising the first pair of wavelengths, and the light reflected therefrom is measured to detect light reflection values corresponding to the first pair of wavelengths. A primary signal is produced which represents a resulting difference between said detected light reflection values, this signal being indicative of the color of the inspected article.
    Type: Grant
    Filed: June 7, 1993
    Date of Patent: February 20, 1996
    Assignee: Centre de Recherche Industrielle du Quebec
    Inventors: Gilles Allaire, Gratien Beauchemin, Roger Garceau, Bruno Leclerc
  • Patent number: 5491349
    Abstract: A semiconductor light emitting device of this invention has more than three light emitting diodes which includes a pair of diodes connected parallel in the reverse direction for each other. A common terminal connecting each one of electrodes of all diodes, the first terminal in which the other electrodes of the diode pair is connected, and the second terminal in which the other electrode of the rest diode is connected, are provide in order to drive the diodes separately.
    Type: Grant
    Filed: April 22, 1994
    Date of Patent: February 13, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Satoshi Komoto, Hiroshi Nagasawa, Hitoshi Kawasaki
  • Patent number: 5491360
    Abstract: An electric packaging arrangement for isolated circuits is described. A lead frame is formed with at least one off-centered tie bar connected between one of the circuits on the lead frame's internal lead and an external handling side rail. The tie bar is off-centered by a specified distance from the longitudinal center line of the package. The external side rail is used to support and align the lead frame during manufacturing. To meet safety requirements, such as the UL-1950 requirements, electrical components in a primary circuit and a secondary circuit are attached and electrically coupled to the lead frame in a manner such that the smallest internal distance between internal circuits is at least a predefined distance. The external distance between the tie bar, connected to the secondary circuit, and the closest primary circuit pin is set to meet external circuit component spacing requirements for isolated circuits.
    Type: Grant
    Filed: December 28, 1994
    Date of Patent: February 13, 1996
    Assignee: National Semiconductor Corporation
    Inventor: Peng-Cheng Lin
  • Patent number: 5489790
    Abstract: An SRAM cell includes a pair of cross-coupled inverters where each inverter includes vertical n-channel and p-channel transistors having a gate electrode that is shared between the transistors that make up each inverter. The gate electrodes for the inverters laterally surround the channel regions of the p-channel load transistors to achieve a relatively high beta ratio without occupying a large amount of substrate surface area. Also, the gate electrodes increase the amount of capacitance of the storage nodes and decreases the soft error rate. The active regions of the latch transistors are electrically isolated from the substrate by a buried oxide layer, thereby decreasing the chances of latch-up.
    Type: Grant
    Filed: January 30, 1995
    Date of Patent: February 6, 1996
    Assignee: Motorola, Inc.
    Inventor: Craig S. Lage
  • Patent number: 5489793
    Abstract: There are provided a plurality of standard cell blocks (2) within an IC chip (1), and an aluminium wiring layer is formed in an aluminium wiring region (8) provided between the standard cell blocks (2) to electrically connect the standard cell blocks (2) to each other. An n-type epitaxial region (4), a p-type diffusion region (5) and an n-type diffusion region (6) are incorporated in an underlayer of the aluminium wiring region (8), to thereby form an evaluation device which is an npn bipolar transistor under the aluminium wiring region (8). A semiconductor device which is capable of accurately evaluating its finished product by the inspection of the evaluation device is provided without the damage of an integration level.
    Type: Grant
    Filed: July 8, 1994
    Date of Patent: February 6, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takuo Matsusako, Kazumasa Satsuma
  • Patent number: 5489801
    Abstract: An integrated circuit package which contains a heat slug that extends from an integrated circuit to a top surface of a surrounding housing. The heat slug has a coefficient of thermal expansion that matches the coefficients of thermal expansion of the housing and the integrated circuit to reduce thermal stresses in the package.
    Type: Grant
    Filed: January 12, 1995
    Date of Patent: February 6, 1996
    Assignee: Intel Corporation
    Inventor: Richard C. Blish, II
  • Patent number: 5488254
    Abstract: A plastic-molded-type semiconductor device is designed to prevent interfaces of a heat conductive member for heat radiation and plastic encapsulant from being separated from each other. The device is of a structure in which the heat conductive member for heat radiation is provided on and thermally connected to one side of a semiconductor chip, and the whole chip and the whole or a part of side surfaces of the heat conductive member are covered with the resin, the opposite side of the heat conductive member being exposed. In this structure, that portion of the heat conductive member which is covered with the resin has a cross-section whose configuration is any one of a circle, an ellipse, a polygon with corner portions whose internal angle is less than 180 degrees and a dull angle or which are rounded to have a low curvature.
    Type: Grant
    Filed: March 29, 1994
    Date of Patent: January 30, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Asao Nishimura, Makoto Kitano, Ichio Shimizu
  • Patent number: 5488242
    Abstract: In a DRAM having a structure in which a storage node electrode is formed via an insulator film in a trench formed in a memory cell region to thereby form a capacitor, and in which the storage node electrode is connected in the source/drain regions of a MOSFET through a storage node contact formed in a part of the insulator film, the trench is disposed so as to deviate widthwise in a channel region of the MOSFET, so that the distance between adjacent element regions is reduced without causing misalignment of masks used in the formation of the storage node contact, thereby to provide a miniaturized high-reliability DRAM. In addition, the storage node contact and the trench can be formed in large size.
    Type: Grant
    Filed: November 24, 1993
    Date of Patent: January 30, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazumasa Sunouchi, Hiroshi Takato, Tohru Ozaki, Naoko Okabe, Katsuhiko Hieda, Fumio Horiguchi, Akihiro Nitayama, Takashi Yamada, Kouji Hasimoto, Satosi Inoue
  • Patent number: 5488251
    Abstract: A photosensor includes a semiconductor substrate of a first-conductivity type with a photoelectric conversion element such as photodiode thereon. The photodiode has a second, opposite conductivity and is surrounded at all of the bottom and sides by a domain having the second conductivity and a high impurity concentration. A first-conductivity domains forms a junction with the second-conductivity domain, and the photodiode is separated from other semiconductor elements by a first-conductivity domain.
    Type: Grant
    Filed: August 3, 1994
    Date of Patent: January 30, 1996
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hidemasa Mizutani, Shigeki Kondo
  • Patent number: 5486926
    Abstract: A method and device is disclosed wherein a subject is excited by electromagnetic radiation in a locally limited range to emit radiation that is not coherent with the exciting radiation. The radiation of atoms lying close to one another on the surface of the subject is not correlated, i.e., the excited point of light radiates incoherently in space, and generally also in time. Since only this incoherent radiation emitted by the point of light is analyzed in distance determination, no speckle structure occurs in the point of light, which makes it possible more accurately to find the position of the point of light and thus also to find the distance much more accurately.
    Type: Grant
    Filed: March 1, 1993
    Date of Patent: January 23, 1996
    Assignee: MAHO Aktiengesellschaft
    Inventor: Gerd Hausler
  • Patent number: 5486707
    Abstract: An antifuse for programmable integrated circuit devices is formed above a refractory metal on a thin native oxide layer and comprises an amorphous compound resulting from an PECVD deposition using a combination of silane gas and nitrogen. After formation of the amorphous antifuse layer, the layer is implanted with an atomic species such as argon. The thin oxide layer is formed on the surface of a refractory metal, therefore the process of forming the oxide is slow, the oxide is of even thickness, and the thickness can be controlled precisely. In a preferred embodiment, a second thin oxide layer is formed above the doped amorphous layer. The oxide layers significantly reduce the leakage current of an unprogrammed antifuse. Because of these thin oxide layers and the implantation step, the amorphous layer may be as thin as 200 .ANG..
    Type: Grant
    Filed: January 10, 1994
    Date of Patent: January 23, 1996
    Assignee: Xilinx, Inc.
    Inventors: Kevin T. Look, Evert A. Wolsheimer
  • Patent number: 5485039
    Abstract: A semiconductor device includes a semiconductor substrate having a pair of opposed main surfaces with a wiring conductor provided on one of the main surfaces; the substrate having at least one through hole extending therethrough so as to be perpendicular to the main surfaces; at least one electrically conductive pin provided on the other of the main surfaces at a position of the at least one through hole, and an adhesive filled into the at least one through hole for fixing the at least one conductive pin to the substrate, wherein the at least one conductive pin is connected electrically through the corresponding at least one through hole to the wiring conductor to transmit/receive an electrical signal to/from an external circuit.
    Type: Grant
    Filed: December 14, 1992
    Date of Patent: January 16, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Yuuji Fujita, Kenichi Mizuishi
  • Patent number: 5485033
    Abstract: A semiconductor device including a vertical transistor, for example of the pnp type, having a p-type substrate (1) which forms the collector, with at its surface an epitaxial n-type layer (3) in which a p-type emitter region (15, 16) is formed, while the portion (9) of the epitaxial layer (3) lying between the emitter (15, 16) and the collector (1) forms the base. In this vertical transistor, the current gain is very strongly increased when the emitter is formed by a first partial emitter region which is weakly p-type doped and which extends below an insulating layer (6) and by a second partial emitter region (16) which is strongly p.sup.++ -type doped and which extends below the contact zone (26) of the emitter defined by an opening in the insulating layer (6). The respective thicknesses and doping levels of the first (15) and second (16) emitter regions are provided such that the first region is transparent to electrons and the second forms a screen against electrons.
    Type: Grant
    Filed: May 25, 1995
    Date of Patent: January 16, 1996
    Assignee: U.S. Philips Corporation
    Inventor: Pierre Leduc
  • Patent number: 5483100
    Abstract: An integrated circuit package, and a method for forming the integrated circuit package, including a single layer or multilayer substrate in which interconnection vias are formed is described. Laser energy is swept across a surface of a mask in which holes have been formed. Laser energy passing through the holes of the mask forms vias in a substrate held in place below the mask. The laser energy is swept at such a speed and is maintained at such an energy level that the laser energy forms vias in the substrate, but does not penetrate a set of leads attached to the substrate. Vias may be formed in this way by either a mask imaging, contact mask or conformal mask technique. The laser energy is emitted from a non-thermal (e.g., excimer) laser. The substrate is formed of an organic (e.g., epoxy) resin. The resin may include reinforcing fibers (e.g., aramid fibers). Substrates may be formed on one or both sides of the set of leads.
    Type: Grant
    Filed: June 2, 1992
    Date of Patent: January 9, 1996
    Assignees: Amkor Electronics, Inc., Teijin Limited
    Inventors: Robert C. Marrs, Tadashi Hirakawa
  • Patent number: 5483342
    Abstract: An interferometer that is used with a frequency shifting phase conjugate mirror (PCM), to produce a 90.degree. polarization rotation, employs only two adjustable elements: a specially shaped prism, and a beam deflector that is preferably a porro prism. The primary prism is shaped and oriented so that a linearally polarized input beam is divided into ordinary (o) and extraordinary (e) subbeams. One of the subbeams is refracted out of the prism along a controlled length path, and then returned back into the prism by the deflector. The second subbeam is retained within the prism by total internal reflection, and directed onto a exit path that coincides with the path of the first subbeam after its reentry into the prism. The recombined output beam is directed into the PCM, from which it is reflected back into the prism for a reverse pass. The difference in path lengths between the o and e subbeams is selected to produce a net 90.degree. polarization rotation after both passes.
    Type: Grant
    Filed: June 25, 1993
    Date of Patent: January 9, 1996
    Assignee: Hughes Aircraft Company
    Inventor: David A. Rockwell