Abstract: Active semiconductor devices including heterojunction diodes and thin film transistors are formed by PECVD deposition of a boron carbide thin film on an N-type substrate. The boron to carbon ratio of the deposited material is controlled so that the film has a suitable band gap energy. Boron carbides such as B.sub.4.7 C, B.sub.7.2 C and B.sub.19 C have suitable band gap energies between 0.8 and 1.7 eV. The stoichiometry of the film can be selected by varying the partial pressure of precursor gases, such as nido pentaborane and methane. The precursor gas or gases are energized, e.g., in a plasma reactor. The heterojunction diodes retain good rectifying properties at elevated temperature, e.g., up to 400.degree. C.

Abstract: A semiconductor integrated circuit device designed with CAD is formed of a plurality of standard cells including at least four I/O terminals. Each standard cell includes a metal interconnection for a power supply and a metal interconnection for the ground, and also includes an active element formation region and a metal interconnection layer isolated from respective interconnection layers and coupled to a plurality of I/O terminals at a position above it. If it is desired to use the metal interconnection as a power signal line, a via hole is formed in an insulator film, and the metal interconnection layer and the metal interconnection for the power supply are coupled together therethrough.

Abstract: A semiconductor device, comprising a transistor, a constant voltage diode having a first end of a first conductivity type connected to an emitter of the transistor and a second end of a second conductivity type, a reverse current preventive diode having a first end of the first conductivity type connected to a collector of the transistor and a second end of the second conductivity type connected to the second end of the constant voltage diode, and a high speed diode reverse-bias connected between the transistor collector and the emitter of the transistor.

Abstract: An array type semiconductor device (10 and 40) has compliant polymer columnar I/O connections (30) to accommodate thermally induced stress during device operation. The device has a semiconductor die (22) mounted to a substrate (12) and electrically connected thereto. A package body (28, 46) covers the semiconductor die and electrical connections (26, 42) to provide mechanical protection. The I/O contacts are formed from a polymer core (34) that is metallized to impart electrical conductivity to the contacts. The metallization (36, 38) may either be a plating around the polymer core or fillers embedded in the polymer. The aspect ratio of the polymer contacts is greater than one to provide compliance while maintaining high I/O density in the array. The metallized polymer contacts may be attached to the package substrate and to a PWB with joints (32) composed of either solder or a conductive adhesive.

Abstract: The semiconductor electronic component comprises, within a semiconductor substrate (3), a first active region (2,4) having a first type of conductivity (n, n.sup.++), and a second active region (10), having a second type of conductivity (p, p.sup.++), opposite that of the first type, located between the first active region (2) and the upper face (5) of the substrate. A projecting region (6), containing a third active region (7, 8) having the first type of conductivity (n.sup.+, n.sup.++) and surmounting a first part (10a) of the second active region, is provided on the upper face of the substrate. Metallizations (13, 14, 15) are respectively located in contact with the three active regions (4, 10e, 7). The second active region includes a depletable semiconductor zone (Z) extending outside the first part (10a) of the second active region, and between the first active region (2) and the upper face (5) of the substrate.

Abstract: Disclosed herein is an insulated-gate thyristor comprising a base layer of a first conductivity type, having first and second major surfaces, a first main-electrode region of the first conductivity type, formed in the first major surface of the base layer, a second main-electrode region of a second conductivity type, formed in the second major surface of the base layer, at least a pair of grooves extending from the first main-electrode region into the base layer, and opposing each other and spaced apart by a predetermined distance, insulated gate electrodes formed within the grooves, and a turn-off insulated-gate transistor structure for releasing carriers of the second conductivity type from the base layer.

Abstract: A semiconductor integrated circuit device of this invention includes a semiconductor substrate having an active region arranged in a main surface area and an inactive region arranged in a peripheral portion of the main surface area. A semiconductor integrated circuit is formed in the active region in the main surface area of the semiconductor substrate. A connection electrode is formed on the inactive region. One end of a lead is connected to the connection electrode and the other end thereof is arranged to extend to the exterior of the semiconductor substrate. The semiconductor integrated circuit and the connection electrode are electrically connected to each other via an impurity diffusion region. At least the active region of the semiconductor substrate, the connection electrode, part of the lead arranged on the main surface of the semiconductor substrate, and the impurity diffusion region are covered with a sealing body having a sealing substrate.

Abstract: There is disclosed a semiconductor device wherein a mounting substrate (3) including an insulating layer and a pattern electrode selectively provided on the insulating layer is mounted on a heat sink (6) having a major surface. A plurality of copper supports (2) each having a surface forming an angle of substantially not more than 90.degree. with the major surface of the heat sink (6) are provided on the mounting substrate (3) such that the respective surfaces are not opposed to each other, and each of the supports (2) supports a semiconductor body (1). The semiconductor bodies (1) are connected to the pattern electrode with wires (9), and a portion enclosing at least the wires (9) is filled with a silicone gel (11). This permits the semiconductor device of large capacity to be reduced in size and to have an improved durability.

Abstract: The parallelism of two nominally parallel surfaces is determined by placing a planar reflector (50) on one surface and a cube beam splitter (52) on the other surface. The reflector is placed to reflect light in a direction normal to the plane of the reflector. The cube beam splitter is placed to reflect part of the light striking a first face (54) back in the opposite direction. The cube beam splitter also reflects part of the incident light towards the reflector so that the reflector reflects the light back to the cube beam splitter, causing the light to exit the first cube beam splitter face. An autocollimator (10) is provided to direct a beam of light (24) into the first face (54) of the cube beam splitter (52) and to display the divergence between the first and second reflected beam portions, the divergence corresponding to the degree of non-parallelism between the two surfaces.

Abstract: A semiconductor device comprises a silicon substrate, a gate electrode including a conductive layer formed on the silicon substrate with a gate insulating film disposed between the conductive layer and the silicon substrate and a first insulating layer covering the conductive layer, a conductive region formed in the surface of the silicon substrate at its portion adjacent to the gate electrode, a second insulating layer formed so as to cover the gate electrode and the silicon substrate, a third insulating layer formed so as to cover the second insulating layer, a contact hole formed by etching to penetrate the third and second insulating layers and to reach the conductive region, and a wiring layer formed to cover the third insulating layer and having a contact part extending inside the contact hole, and electrically connect to the conductive region, the second insulating layer being made of a material having a selected ratio of an etching rate relative to an etching rate of a material of the first insulating

Abstract: A plurality of semiconductor arrangements arranged on interconnects are cected parallel to one another in a module. The arrangements lie opposite one another in pairs. At least one pair and at most two pairs of semiconductor arrangements are arranged to follow one another in the direction of an axis of the module and are further connected to lead conductors. Positions of the lead conductors with respect to the contacted semiconductor arrangements are the same for each pair of semiconductor arrangements or, respectively, two respective pairs of semiconductor arrangements. Corresponding lead conductors are connected to one another above the interconnects.

Abstract: A focused light beam instrument measures characteristics of webs of sheet material. The instrument and a reference surface, a backing tile in a carousel, are on opposite sides of the web which is maintained a fixed distance from the reference surface by a Bernoulli hold down device such that variations in the gap affect the beam focus. The instrument and reference surface scan the web via a scanning frame. The instrument is calibrated-standardized in an off sheet position where a first surface, a carousel backing tile, is moved opposite to the instrument and in the plane of the web. The instrument measures the first surface and a second surface, another carousel backing tile, which is moved opposite to the instrument but spaced farther from or closer thereto than the first surface. The distance of the instrument from the web is calculated from the difference between the measurements of the first and second surfaces.

Abstract: A new and improved integrated circuit cooling apparatus includes a heat-conductive base plate to be placed against an integrated circuit, a Peltier Effect cooling module having a cooling side connected to a top surface of the heat-conductive base plate, a heat radiator assembly connected to a heating side of the Peltier Effect cooling module, and a fan assembly juxtaposed next to a heat-radiating portion of the heat radiator assembly. The Peltier Effect cooling module cools the integrated circuit, and the fan assembly cools heat radiated from the heat radiator assembly. The heat radiator assembly can include threaded channels, and the fan assembly includes connection apertures adapted to be placed in registration with the threaded channels of the heat radiator assembly. Threaded connectors, such as screws, arc adapted to connect to the threaded channels to connect the fan assembly to the heat radiator assembly.

Abstract: The disclosure relates to a semiconductor device comprising silicon having a substrate composed of low grade silicon, a silicon layer whose silicon purity is higher than that of the low grade silicon formed on the substrate and an electrode formed on the silicon layer. In the device, the low grade silicon may be selected from metallurgical grade silicon and silicon whose purity is less than 99.99%, and the silicon layer may be over 99.999% purity or semiconductor grade.

Abstract: A plastic package type semiconductor device is composed of a rolled metal substrate made of copper or copper alloy and an insulating film formed on the surface of the substrate. The film may be a single-layer film made of silicon oxynitride or a composite film formed by laminating a silicon oxide layer and a silicon oxynitride layer (or a silicon nitride layer). A semiconductor element is mounted on the film or on the exposed surface of the substrate. Other passive elements are provided on the film. After connecting these elements with bonding wires, the entire device is sealed in a resin molding. This device is thus free of cracks due to difference in thermal expansion between the film and the substrate, or peeling due to moisture absorption.

Abstract: A thyristor includes a semiconductor body with a surface. The semiconductor body has an inner zone of a first conduction type; a cathode-side base zone of a second conduction type opposite the first type, the base zone having a recess formed therein; a layer of the second conduction type being disposed on the surface of the semiconductor body, being disposed in the cathode-side base zone, being thinner than the cathode-side base zone, and being joined to the cathode-side base zone; and an additional zone of the second conduction type being disposed in the recess, being joined to the layer, being thicker than the layer, and being spaced apart from the cathode-side base zone.

Abstract: A high frequency, high power transistor is vertically isolated by providing a thermally conductive, electrically insulating substrate, upon which the transistor components (including collector, base, and emitter) are grown, positioned directly on the heat sink and a planar top surface formed on the transistor by the base metal contact, the emitter metal contact, and the collector metal contact. Vertical isolation improves the thermal management capabilities of the transistor. Moreover, such a vertically isolated transistor is well-adapted for lateral isolation, which solves the capacitance problems inherent in conventional devices.

Abstract: A cooling device formed in a thermally conductive substrate having at least one microchannel of dimensions that induce capillary action and a surface in thermal contact with a heated region. The microchannel has a longitudinal opening oriented away from the heated region and is supplied with liquid coolant which is contained by a meniscus near the opening. The coolant vaporizes at the meniscus and absorbs heat but, due to increased pressure in the coolant contained by the meniscus, does not boil within the microchannel, allowing more liquid coolant contact with the thermally conductive substrate and walls. The vaporized coolant is discharged into a chamber facing the opening which can be at a lower pressure to remove additional heat by gaseous expansion. The discharge of gaseous coolant allows the capillary flow of the liquid coolant in the microchannels to be unimpeded, and may be augmented by a fluid pump.

Abstract: An interferometer amplitude modulation reduction circuit coupled to receive an interferometer output signal from the output of a fiber optic interferometer sensor. The interferometer sensor is excited by a frequency modulated input light signal from a light source having an unwanted amplitude modulation and intensity noise signal component. The interferometer output signal has both wanted interference induced intensity modulation and also unwanted amplitude modulation and intensity noise from the unwanted amplitude modulation and intensity noise signal components present on the frequency modulated input light signal. The invention circuit has a sampling means for sampling a sample portion of the frequency modulated input light signal from the output of the light source. The sampling means detects and the sample portion signal to provide a detected sample intensity signal having a detected unwanted amplitude modulation and intensity noise signal component.

Abstract: A multi-chip module semiconductor device including a plurality of IC chips arranged in a side-by-side relationship on a supporting member such as a tab is provided. Each of the IC chips is provided with an array of bonding pads for connection with the exterior of the device only along such side to which no other IC chip is disposed adjacent thereto.