Abstract: The present invention relates to a flexible organic EL device comprising, on one of the surfaces of an organic resin base, an inorganic protective layer, an organic EL light emitting part, a buffer layer, and a breakage-resistant layer in this order, wherein the buffer layer is a silicone or EPDM containing layer and an elastic modulus of the breakage-resistant layer at 5 to 35° C. is 100 MPa to 300 GPa.

Abstract: An organic memresitor/memcapacitor comprises of two terminal electrodes, each electrode has a membrane made of nanostructure organic conducting polymer of cyclodextrin derivatives attached thereto.

Abstract: The present disclosure provides an array substrate and a method of manufacturing the same, and a display panel comprising the array substrate, for reducing a drop or height difference between surfaces of portions of a passivation layer located on either side of a source/drain electrode lead wire and a surface of a portion of passivation layer located on an upper surface of the source/drain electrode lead wire so as to increase an aperture ratio of the display panel. The method comprises: forming a source/drain electrode lead wire and a passivation layer successively on a base substrate, the passivation layer at least covering the source/drain electrode lead wire; and thinning a portion of the passivation layer located on the source/drain electrode lead wire such that a surface of the portion is higher than those of other portions of the passivation layer, at the time of patterning the passivation layer to form a via hole therein.

Abstract: A package component includes a surface dielectric layer including a planar top surface, a metal pad in the surface dielectric layer and including a second planar top surface level with the planar top surface, and an air trench on a side of the metal pad. The sidewall of the metal pad is exposed to the air trench.

Abstract: A repairable matrix-addressed system includes a system substrate, an array of electrically conductive row lines, and an array of electrically conductive column lines disposed over the system substrate. The row lines extend over the system substrate in a row direction and the column lines extend over the system substrate in a column direction different from the row direction to define an array of non-electrically conductive intersections between the row lines and the column lines. An array of electrically conductive line segments is disposed over the system substrate. The line segments extend over the system substrate substantially parallel to the row direction and have a line segment length that is less than the distance between adjacent column lines. Each line segment is electrically connected to a column line. One or more devices are electrically connected to each row line and to each line segment adjacent to the row line.

Abstract: A light emitting element with a hexagonal planar shape, has: an n-side semiconductor layer; a p-side semiconductor layer provided on the n-side semiconductor layer; a plurality of holes that are provided to an area excluding three corners at mutually diagonal positions of the p-side semiconductor layer in plan view, and expose the n-side semiconductor layer; a first p-electrode provided in contact with the p-side semiconductor layer; second p-electrodes provided to three corners on the first p-electrode; and an n-electrode that is provided on the first p-electrode and is electrically connected to the n-side semiconductor layer through the plurality of holes.

Abstract: A semiconductor device adopts an isolation scheme to protect low voltage transistors from high voltage operations. The semiconductor device includes a substrate, a buried layer, a transistor well region, a first trench, and a second trench. The substrate has a top surface and a bottom surface. The buried layer is positioned within the substrate, and the transistor well region is positioned above the buried layer. The first trench extends from the top surface to penetrate the buried layer, and the first trench has a first trench depth. The second trench extending from the top surface to penetrate the buried layer. The second trench is interposed between the first trench and the transistor well region. The second trench has a second trench depth that is less than the first trench depth.

Abstract: In one embodiment, a flexible device is provided. The flexible device may include a flexible substrate, a buffer layer, a light reflective layer, and a device layer. The buffer layer is located on the flexible substrate. The light reflective layer is located on the flexible substrate, wherein the light reflective layer has a reflection wavelength of 200 nm˜1100 nm, a reflection ratio of greater than 80%, and a stress direction of the light reflective layer is the same as a stress direction of the flexible substrate. The device layer is located on the light reflective layer and the buffer layer.

Abstract: A chip package structure can include: a lead frame having a carrier substrate and a first lead around the carrier substrate; a first conductive post arranged on the first lead and electrically coupled with the first lead; a first chip having an active face and an inactive face opposite to the active face and attached to the carrier substrate, and electrode pads on the active face are provided with a first electrical connector; a first plastic package configured to fully encapsulate the first chip, and to partly encapsulate the lead frame, where the first plastic package includes a first surface and a second surface opposite to the first surface, where the first conductive post and the first electrical connector are exposed on the first surface, and where the first lead is exposed on the second surface, and a second lead being arranged on the first surface.

Abstract: A semiconductor package and a method of making a semiconductor package. As non-limiting examples, various aspects of this disclosure provide various semiconductor packages, and methods of making thereof, that comprise a conductive layer that comprises an anchor portion extending through at least one dielectric layer.

Abstract: Methods for producing System-in-Packages (SiPs) containing embedded Surface Mount Device (SMD) modules are provided, as SiPs containing SMD modules. In one embodiment, the fabrication method includes positioning a semiconductor die and first preassembled SMD module, which contains a plurality of SMDs soldered to an interposer substrate, in predetermined spatial relationship. The preassembled SMD module and the semiconductor die are overmolded to yield a molded panel having a frontside at which the first preassembled SMD module and the semiconductor die are exposed. A Redistribution Layer (RDL) structure can be formed over the frontside of the molded panel containing interconnect lines electrically coupling the semiconductor die and the first preassembled SMD module. The molded panel may then undergo singulation to produce an SiP having a molded body in which the semiconductor die and the first preassembled SMD module are embedded.

Abstract: A method of lead frame surface modification includes providing at least one pre-fabricated metal lead frame or package substrate (substrate) unit including a base metal having a die pad and a plurality of contact regions surrounding the die pad. An ink including a material that is a solid or a precursor for a solid that forms a solid upon a curing step or a sintering step that removes a liquid carrier is additively deposited including onto at least one of (i) a region of the die pad and (ii) at one region of at least a first of the contact regions (first contact region). The ink is sintered or cured to remove the liquid carrier so that a substantially solid ink residue remains.

Abstract: A semiconductor memory device of an embodiment comprises a memory cell. This memory cell comprises: an oxide semiconductor layer; a gate electrode; and a charge accumulation layer disposed between the oxide semiconductor layer and the gate electrode. This oxide semiconductor layer includes a stacked structure of an n type oxide semiconductor layer and a p type oxide semiconductor layer.

Abstract: The present invention relates to a high reliability field effect power device and a manufacturing method thereof. A method of manufacturing a field effect power device includes sequentially forming a transfer layer, a buffer layer, a barrier layer and a passivation layer on a substrate, patterning the passivation layer by etching a first region of the passivation layer, and forming at least one electrode on the first region of the barrier layer exposed by patterning the passivation layer, wherein the first region is provided to form the at least one electrode, and the passivation layer may include a material having a wider bandgap than the barrier layer to prevent a trapping effect and a leakage current of the field effect power device.

Abstract: An electronic static discharge protection apparatus provided. A plurality of ESD circuits serially coupled between a pad and a internal circuit, a first stage ESD circuit includes a ESD element directly coupled to the pad, and a last stage ESD circuit includes an inductive element directly coupled to the internal circuit, so as to improve electronic discharge protecting ability of the ESD protection apparatus and increase circuit operation bandwidth without signal loss attenuation.

Abstract: Some embodiments include a transistor having a drain region and a source region. A conductive gate is between the source and drain regions. First channel material is between the gate and the source region. The first channel material is spaced from the gate by one or more insulative materials. Second channel material is between the first channel material and the source region, and directly contacts the source region. The first and second channel materials are transition metal chalcogenide. One of the source and drain regions is a hole reservoir region and the other is an electron reservoir region. Tunnel dielectric material may be between the first and second channel materials.

Abstract: A via opening is provided in an interconnect dielectric material. Prior to line opening formation, a continuous layer of a sacrificial material is formed lining the entirety of the via opening. An organic planarization layer (OPL) and a photoresist that contains a line pattern are formed above the interconnect dielectric material. The line pattern is then transferred into an upper portion of the interconnect dielectric material, while maintaining a portion of the OPL and a portion of the continuous layer of sacrificial material within a lower portion of the via opening. The remaining portions of the OPL and the sacrificial material are then removed from the bottom portion of the via opening. A combined via opening/line opening is provided in which the via opening has a well controlled profile/geometry. An interconnect metal or metal alloy can then be formed into the combined via opening/line opening.

Abstract: An organic light-emitting component (100) is specified, which comprises a carrier (1) and an organic layering sequence (2) arranged on the carrier (1). The organic layering sequence (2) comprises at least two organic layers, wherein at least one of the organic layers is designed as an emitting layer (23). The emitting layer (23) emits light (200) of a first wavelength range, which has an intensity maximum at a first wavelength. Further, the organic light-emitting component (100) comprises an anode (3) and a cathode (4) which provide the electrical contacting of the organic layering sequence (2). Further, the organic light-emitting component (100) has at least one nanoparticle layer (20), wherein one nanoparticle layer (20) is an organic layer of the organic layering sequence (2) provided with first nanoparticles (5). The first nanoparticles (5) have a refractive index (nN) that is smaller than at least one refractive index of an organic material of one of the organic layers.

Abstract: A method of preparing a single crystal semiconductor handle wafer in the manufacture of a silicon-on-insulator device is provided. The method comprises forming a multilayer of passivated semiconductors layers on a dielectric layer of a high resistivity single crystal semiconductor handle wafer. The method additionally comprises forming a semiconductor oxide layer on the multilayer of passivated semiconductor layers. The multilayer of passivated semiconductor layers comprise materials suitable for use as charge trapping layers between a high resistivity substrate and a buried oxide layer in a semiconductor on insulator structure.

Abstract: A superlattice layer including a plurality of periods, each of which is formed from a plurality of sub-layers is provided. Each sub-layer comprises a different composition than the adjacent sub-layer(s) and comprises a polarization that is opposite a polarization of the adjacent sub-layer(s). In this manner, the polarizations of the respective adjacent sub-layers compensate for one another. Furthermore, the superlattice layer can be configured to be at least partially transparent to radiation, such as ultraviolet radiation.