Abstract: A display panel and a display device including the display panel are provided. The display panel includes data lines and scan lines arranged to be intersected, and a sensing antenna. The data lines and the scan lines are located in a display region of the display panel, and define multiple sub-pixels. The sensing antenna includes multiple sensing coils and is at least partly located in the display region of the display panel, and projections of the data lines and/or the scan lines cover projections of the sensing coils in a direction perpendicular to a surface of the display panel, in order to avoid affection on an aperture ratio of the display panel caused by the sensing coils located in the display region.

Abstract: A chip package includes a chip, an insulating layer and a conductive layer. The chip includes a substrate, an epitaxy layer, a device region and a conductive pad. The epitaxy layer is disposed on the substrate, and the device region and the conductive pad are disposed on the epitaxy layer. The conductive pad is at a side of the device region and connected to the device region. The conductive pad protrudes out of a side surface of the epitaxy layer. The insulating layer is disposed below the substrate and extended to cover the side surface of the epitaxy layer. The conductive layer is disposed below the insulating layer and extended to contact the conductive pad. The conductive layer and the side surface of the epitaxy layer are separated by a first distance.

Abstract: An organic light-emitting diode (OLED) display and a method of manufacturing the same are disclosed. In one aspect, the OLED display includes an OLED formed over a substrate, the OLED including a first electrode, a second electrode formed over the first electrode and an intermediate layer interposed between the first and second electrodes. A pixel defining layer is formed over the substrate and adjacent to the OLED, and a protection layer is formed over the second electrode and configured to protect the OLED. A thin-film encapsulating layer is formed over the protection layer and sealing the OLED so as to protect the OLED from the environment, at least a part of the thin-film encapsulating layer contacting the pixel defining layer.

Abstract: The present invention discloses an array substrate, a display panel and a display device. The array substrate includes a substrate, a gate line and a data line arranged on the substrate, and a thin film transistor arranged in an overlapping region where the gate line and the data line are overlapped; wherein an orthogonal projection of the thin film transistor on the substrate covers an orthogonal projection of the overlapping region of the gate line and the data line on the substrate. Because of design of a location of the thin film transistor according to the present invention, the opening ratio can be increased, the slightly rubbing region adjacent to the thin film transistor can be reduced; and, because of the closed channel region, levels at various positions of the thin film transistor can be uniform, and a bigger contact area provided for the supporting post, thereby increasing supporting ability of the supporting post and compressive property of the panel.

Abstract: Provided herein are semiconductor devices with through electrodes and methods of fabricating the same. The methods may include providing a semiconductor substrate having top and bottom surfaces facing each other, forming on the top surface of the semiconductor substrate a main via having a hollow cylindrical structure and a metal line connected to the main via, forming an interlayered insulating layer on the top surface of the semiconductor substrate to cover the main via and the metal line, removing a portion of the semiconductor substrate to form a via hole exposing a portion of a bottom surface of the main via, and forming in the via hole a through electrode that is electrically connected to the main via. The bottom surface of the main via is overlapped by a circumference of the via hole, when viewed in a plan view.

Abstract: A light emitting element manufacturing method of allowing a semiconductor laminated part which includes a light emitting layer and includes a group-III nitride semiconductor to grow on a substrate surface in which protrusions are formed in a period which is larger than an optical wavelength of light emitted from the light emitting layer and is smaller than a coherent length of the light, includes: forming a buffer layer along the substrate surface having the protrusions; allowing crystal nuclei which have facet surfaces and are separated from each other to grow on the buffer layer such that the crystal nuclei include at least one protrusion; and allowing a planarization layer to grow on the buffer layer in which the crystal nuclei are formed.

Abstract: A solid-state imaging device includes a phase detection photodiode, a light shielding film, and a light absorption film. The phase detection photodiode has a light receiving surface. The light shielding film covers a part of the light receiving surface of the phase detection photodiode. The light absorption film is disposed over the phase detection photodiode and over the light shielding film.

Abstract: The present disclosure provides an array substrate and a method of manufacturing the same, and a display panel comprising the array substrate, for reducing a drop or height difference between surfaces of portions of a passivation layer located on either side of a source/drain electrode lead wire and a surface of a portion of passivation layer located on an upper surface of the source/drain electrode lead wire so as to increase an aperture ratio of the display panel. The method comprises: forming a source/drain electrode lead wire and a passivation layer successively on a base substrate, the passivation layer at least covering the source/drain electrode lead wire; and thinning a portion of the passivation layer located on the source/drain electrode lead wire such that a surface of the portion is higher than those of other portions of the passivation layer, at the time of patterning the passivation layer to form a via hole therein.

Abstract: A transistor having high field-effect mobility is provided. A transistor having stable electrical characteristics is provided. A transistor having low off-state current (current in an off state) is provided. Alternatively, a semiconductor device including the transistor is provided. The semiconductor device includes a first insulating film, an oxide semiconductor film over the first insulating film, a second insulating film over the oxide semiconductor film, and a conductive film overlapping with the oxide semiconductor film with the first insulating film or the second insulating film provided between the oxide semiconductor film and the conductive film. The composition of the oxide semiconductor film changes continuously between the first insulating film and the second insulating film.

Abstract: The semiconductor device comprises a semiconductor substrate (1), a photosensor (2) integrated in the substrate (1) at a main surface (10), an emitter (12) of radiation mounted above the main surface (10), and a cover (6), which is at least partially transmissive for the radiation, arranged above the main surface (10). The cover (6) comprises a cavity (7), and the emitter (12) is arranged in the cavity (7). A radiation barrier (9) can be provided on a lateral surface of the cavity (7) to inhibit cross-talk between the emitter (12) and the photosensor (2).

Abstract: An integrated circuit (IC) die including a top surface and a bottom surface, a plurality of spaced apart ground connection traces positioned between the top surface and the bottom surface; with a hole in the die exposing the plurality of spaced apart ground connection traces.

Abstract: A display device includes: a flexible substrate; a pixel over the flexible substrate, the pixel including a transistor and a display element; a first wiring for transmitting a signal to the pixel, the first wiring extending in a first direction; a second wiring extending in a second direction intersecting the first direction; an inorganic insulating layer on a higher level than the first wiring or the second wiring; and an organic insulating layer on a higher level than the inorganic insulating layer, wherein the inorganic insulating layer has an opening exposing a part of the upper surface of the first wiring or the second wiring is exposed, and the organic insulating layer is provided in such a way as to fill the opening.

Abstract: Disclosed is an organic light emitting diode display that includes a display panel having a display area that is defined with X and Y axes intersecting each other; and a plurality of pixels in the display panel, each comprising a first sub-pixel, a second sub-pixel and a third sub-pixel, wherein a shape of each of the first, second and third sub-pixels is defined by sides that are at a non-zero angle to the Y-axis or parallel to the X-axis, the first and second sub-pixels are substantially symmetrical to each other with respect to the X-axis, and the third sub-pixel is larger in size than the first and second sub-pixels.

Abstract: In accordance with an embodiment, semiconductor component having a compound semiconductor material based semiconductor device connected to a silicon based semiconductor device and a protection element, wherein the silicon based semiconductor device is a transistor. The protection element is coupled in parallel across the silicon based semiconductor device and may be a resistor, a diode, or a transistor. In accordance with another embodiment, the silicon based semiconductor device is a diode. The compound semiconductor material may be shorted to a source of potential such as, for example, ground, with a shorting element.

Abstract: Various embodiments relate to a semiconductor package structure. The semiconductor package structure includes a first chip having a first surface and a second surface opposite the first surface. The semiconductor package structure further includes a supporter surrounding an edge of the first chip. The semiconductor package structure further includes a conductive layer disposed over the first surface of the first chip and electrically connected to the first chip. The semiconductor package structure further includes an insulation layer disposed over the first surface of the first chip, wherein the insulation layer extends toward and overlaps the supporter in a vertical projection direction. The semiconductor package structure further includes an encapsulant between the first chip and the supporter and surrounding at least the edge of the first chip.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to interconnect structures and methods of manufacture. The structure includes: a cobalt metallization structure with a modified surface of etch chemistries; a layer of material on the modified surface; and an interconnect structure in direct contact with the material.

Abstract: Self-aligned gate edge and local interconnect structures and methods of fabricating self-aligned gate edge and local interconnect structures are described. In an example, a semiconductor structure includes a semiconductor fin disposed above a substrate and having a length in a first direction. A gate structure is disposed over the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate edge isolation structures is centered with the semiconductor fin. A first of the pair of gate edge isolation structures is disposed directly adjacent to the first end of the gate structure, and a second of the pair of gate edge isolation structures is disposed directly adjacent to the second end of the gate structure.

Abstract: A semiconductor device includes a substrate comprising a channel region and a recess, wherein the recess is located at both side of the channel region; a gate structure formed over the channel region; a first SiP layer covering bottom corners of the gate structure and the recess; and a second SiP layer formed over the first SiP layer and in the recess, wherein the second SiP layer has a phosphorus concentration higher than that of the first SiP layer.

Abstract: An organic light emitting display apparatus includes a substrate, a plurality of organic light emitting elements on the substrate, an encapsulation substrate covering the organic light emitting elements, and a scattering layer including a resin, and a plurality of scattering particles distributed in the resin, and including a variety of particle sizes in a first range from about 500 nm to about 800 nm, wherein ones of the scattering particles having a first particle size include a highest concentration of the scattering particles, and wherein a concentration of other ones of the scattering particles is inversely proportional to a magnitude of a difference in particle size between the other ones of the scattering particles and the ones of the scattering particles having the first particle size.

Abstract: A cost effective process flow for manufacturing semiconductor on insulator structures is parallel is provided. Each of the multiple semiconductor-on-insulator composite structures prepared in parallel comprises a charge trapping layer (CTL).