Abstract: In some examples, a circuit package further includes an insulating layer and a first transistor extending through the insulating layer, where the first transistor includes a first control terminal on a top side of the insulating layer, a first source terminal on the top side of the insulating layer, and a first drain terminal on a bottom side of the insulating layer. The circuit package includes a second transistor extending through the insulating layer, where the second transistor includes a second control terminal on the top side of the insulating layer, a second source terminal on the bottom side of the insulating layer, and a second drain terminal on the top side of the insulating layer.

Abstract: A transistor in which a change in characteristics is small is provided. A circuit, a semiconductor device, a display device, or an electronic device in which a change in characteristics of the transistor is small is provided. The transistor includes an oxide semiconductor; a channel region is formed in the oxide semiconductor; the channel region contains indium, an element M, and zinc; the element M is one or more selected from aluminum, gallium, yttrium, tin, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium; a gate insulator contains silicon and oxygen whose atomic number is 1.5 times or more as large as the atomic number of silicon; the carrier density of the channel region is higher than or equal to 1×109 cm?3 and lower than or equal to 5×1016 cm?3; and the energy gap of the channel region is higher than or equal to 2.7 eV and lower than or equal to 3.1 eV.

Abstract: The present invention provides a thin-film transistor in which transistor characteristics such as drain current and threshold voltage are improved, and a method of manufacturing the same. The present invention provides a thin-film transistor provided with a source electrode (108), a drain electrode (109), a semiconductor layer (105), a gate electrode (103), and an insulating layer (104); wherein the semiconductor layer (105) contains a composite metal oxide obtained by adding to a first metal oxide an oxide having an oxygen dissociation energy that is at least 200 kJ/mol greater than the oxygen dissociation energy of the first metal oxide, whereby the amount of oxygen vacancy is controlled; and the insulating layer (104) is provided with an SiO2 layer, a high-permittivity first layer, and a high-permittivity second layer, whereby the dipoles generated at the boundary between the SiO2 layer and the high-permittivity layers are used to control the threshold voltage.

Abstract: Provided are methods of forming sealed via structures. One method involves: (a) providing a semiconductor substrate having a first surface and a second surface opposite the first surface; (b) forming a layer on the first surface of the substrate; (c) etching a via hole through the substrate from the second surface to the layer, the via hole having a first perimeter at the first surface; (d) forming an aperture in the layer, wherein the aperture has a second perimeter within the first perimeter; and (e) providing a conductive structure for sealing the via structure. Also provided are sealed via structures, methods of detecting leakage in a sealed device package, sealed device packages, device packages having cooling structures, and methods of bonding a first component to a second component.

Abstract: The organic electroluminescence display device of an embodiment of the present invention includes a substrate, a plurality of pixels formed on the substrate, and a sealing film that covers the plurality of pixels. The sealing film includes a first barrier layer, a base layer covering the top surface of the first barrier layer, an inter layer locally formed on the top surface of the base layer, and a second barrier layer covering the top surface of the base layer and the top surface of the inter layer. The inter layer is formed so as to cover a step on the top surface of the base layer.

Abstract: A fault tolerant design for large area nitride semiconductor devices is provided, which facilitates testing and isolation of defective areas. A transistor comprises an array of a plurality of islands, each island comprising an active region, source and drain electrodes, and a gate electrode. Electrodes of each island are electrically isolated from electrodes of neighboring islands in at least one direction of the array. Source, drain and gate contact pads are provided to enable electrical testing of each island. After electrical testing of islands to identify defective islands, overlying electrical connections are formed to interconnect source electrodes in parallel, drain electrodes in parallel, and to interconnect gate electrodes to form a common gate electrode of large gate width Wg. Interconnections are provided selectively to good islands, while electrically isolating defective islands. This approach makes it economically feasible to fabricate large area GaN devices, including hybrid devices.

Abstract: An organic light emitting display device includes a plurality of pixel regions on a substrate, each having a sub-pixel region, a transmissive region and a peripheral region, a plurality of sub-pixel circuits in the sub-pixel region that control the sub-pixel region, a planarization layer that covers the sub-pixel circuits, a first electrode disposed on the planarization layer in the sub-pixel region, a second electrode disposed on the first electrode, and a plurality of wirings disposed at different levels over the substrate in the peripheral region. The wirings are arranged in at least double level configuration and include first wirings that extend in a first direction over the substrate, and second wirings that extend over the substrate in a second direction substantially perpendicular to the first direction.

Abstract: A light-emitting display device comprises: a substrate including a plurality of pixel areas arranged in a first direction and a second direction intersecting the first direction; a first electrode on the substrate in each of the plurality of pixel areas; a plurality of pixels corresponding to the first electrode in each of the plurality of pixel areas; a pixel defining layer on the substrate having a pixel opening exposing the first electrode; a lens layer on the first electrode in the pixel opening, a thickness in a center of the lens layer being different from a thickness at an edge of the lens layer; a planarization layer on the lens layer in the pixel opening and having a flat surface facing away from the lens layer; a light emitting layer on the planarization layer; and a second electrode on the light emitting layer.

Abstract: A transistor with a multi-layer active layer having at least one partial recess is provided. The transistor includes a channel layer arranged over a substrate. The channel layer has a first bandgap. The transistor includes a first active layer arranged over the channel layer. The first active layer has a second bandgap different from the first band gap such that the first active layer and the channel layer meet at a heterojunction. The transistor includes a second active layer arranged over the first active layer. The transistor also includes a dielectric layer arranged over the second active layer. The transistor further includes gate electrode having gate edges that are laterally adjacent to the dielectric layer. At least one gate edge of the gate edges is laterally separated from the second active layer by a first recess.

Abstract: An approach to provide an electronic assembly process that includes receiving at least one electronic assembly after a solder reflow process using a Sn-containing solder and a water-soluble flux. The approach includes baking the at least one electronic assembly in an oxygen containing environment and, then cleaning the at least one electronic assembly in an aqueous cleaning process.

Abstract: An image sensor structure that includes a first semiconductor substrate having a plurality of imaging sensors; a first interconnect structure formed on the first semiconductor substrate; a second semiconductor substrate having a logic circuit; a second interconnect structure formed on the second semiconductor substrate, wherein the first and the second semiconductor substrates are bonded together in a configuration that the first and second interconnect structures are sandwiched between the first and second semiconductor substrates; and a backside deep contact (BDCT) feature extended from the first interconnect structure to the second interconnect structure, thereby electrically coupling the logic circuit to the image sensors.

Abstract: A display panel including: a substrate; and a plurality of line banks arranged along a specific direction on the substrate, wherein the line banks are each formed of plural line segments connected to one another end to end, and each have a periodic structure.

Abstract: A two-dimensional heterostructure is synthesized by producing a patterned first two-dimensional material on a growth substrate. The first two-dimensional material is patterned to define at least one void through which an exposed region of the growth substrate is exposed. Seed molecules are selectively deposited either on the exposed region of the growth substrate or on the patterned first two-dimensional material. A second two-dimensional material that is distinct from the first two-dimensional material is then grown from the deposited seed molecules.

Abstract: The organic electroluminescence display device of an embodiment of the present invention includes a substrate, a plurality of pixels formed on the substrate, and a sealing film that covers the plurality of pixels. The sealing film includes a first barrier layer, a base layer covering the top surface of the first barrier layer, an inter layer locally formed on the top surface of the base layer, and a second barrier layer covering the top surface of the base layer and the top surface of the inter layer. The inter layer is formed so as to cover a step on the top surface of the base layer.

Abstract: A method of fabricating a light emitting diode, which includes an n-type contact layer and a light generating structure adjacent to the n-type contact layer, is provided. The light generating structure includes a set of quantum wells. The contact layer and light generating structure can be configured so that a difference between an energy of the n-type contact layer and an electron ground state energy of a quantum well is greater than an energy of a polar optical phonon in a material of the light generating structure. Additionally, the light generating structure can be configured so that its width is comparable to a mean free path for emission of a polar optical phonon by an electron injected into the light generating structure.

Abstract: A manufacturing method of a thin film transistor array panel according to an exemplary embodiment of the present invention includes forming an amorphous silicon thin film on a substrate. A lower region of the amorphous silicon thin film is crystallized to form a polycrystalline silicon thin film by irradiating a laser beam with an energy density of from about 150 mj/cm2 to about 250 mj/cm2 to the amorphous silicon thin film.

Abstract: A multilayer structure for a semiconductor device and a method of forming a multilayer structure for a semiconductor device. The multilayer structure comprises: a substrate having an electrically conductive portion thereon; a dielectric layer formed over the substrate; the dielectric layer comprising an opening over at least part of the electrically conductive portion; and a conductive pillar formed on the at least part of the electrically conductive portion; wherein the conductive pillar comprises walls defined by at least the opening of the dielectric layer and an opening of a patterned layer.

Abstract: A display may have an array of pixels formed from organic light-emitting diodes and thin-film transistor circuitry. A planarization layer may be interposed between the thin-film transistor circuitry and the organic light-emitting diodes. To protect the organic light-emitting diodes from photoactive compounds that may be outgassed from the planarization layer, an inorganic barrier layer may be interposed between the planarization layer and the organic light-emitting diodes. The inorganic barrier layer may be formed on top of and/or below a pixel definition layer that defines light-emitting zones for the organic light-emitting diodes. In another suitable arrangement, the inorganic barrier layer may itself define light-emitting zones and may be used in place of a polymer-based pixel definition layer. The inorganic barrier layer may include trenches in which the emissive material of the light-emitting diodes is formed.

Abstract: An organic electroluminescence (EL) device whose organic EL layer is less likely exposed to moisture. The organic EL device includes an organic EL layer; and a hygroscopic layer disposed with respect to at least one main surface of the organic EL layer. The hygroscopic layer includes: a hygroscopic film containing a base material and a hygroscopic agent mixed in the base material; and a pair of covering films each covering a different one of surfaces of the hygroscopic film in a thickness direction of the hygroscopic film. A region of the hygroscopic film that is in contact with one covering film whose distance from the organic EL layer is smaller than a distance of the other covering film from the organic EL layer contains the hygroscopic agent at a content rate lower than an average content rate of the hygroscopic agent in the hygroscopic film.

Abstract: Provided are liquid crystal display and the method for manufacturing the same. According to an aspect of the present disclosure, there is provided a liquid crystal display device, including: a first substrate; a gate electrode disposed on the first substrate; a semiconductor pattern layer disposed on the gate electrode; and a source electrode and a drain electrode disposed on the semiconductor pattern layer and facing each other, wherein the gate electrode includes a reference plane and a protrusion protruding from the reference plane in a horizontal direction, and the protrusion overlaps the source electrode and the drain electrode.