Abstract: A test board for testing a semiconductor device. The semiconductor device includes at least first and second input terminals and an input/output buffer cell for buffering a signal obtained from the first input terminal to output an internal signal. The operation of the semiconductor device is controlled by a signal obtained from the second input terminal. The test board includes a first delay element for delaying a signal to be transmitted therethrough for a first signal propagation delay time and a second delay element for delaying a signal to be transmitted therethrough for a second signal propagation delay time different from the first signal propagation delay time.
Abstract: A digital eddy current proximity system including a digital impedance measuring device for digitally measuring the proximity probes impedance correlative to displacement motion and position of a metallic target object being monitored. The system further including a cable-length calibration method, an automatic material identification and calibration method, a material insensitive method, an inductive ratio method and advanced sensing characteristics.
Abstract: A moisture meter (1) has an LCD display (8) driven by a digital microcontroller (50) which generates digital moisture reading data. Readings are stored as discrete records in files. The microcontroller (51) stores a library of material data and automatically compensates signals from a capacitive/impedance sensor circuit (51) according to both stored material parameter values and sensed temperature. Users may edit the parameter values. A non-removable cover (4) is used at the final stage of production to configure the meter for the nature of interfacing (such as serial port interfacing) required.
Type:
Grant
Filed:
February 23, 2000
Date of Patent:
January 22, 2002
Assignee:
Rynhart Research Limited
Inventors:
Alan Rynhart, John Fallon, James McIlroy, Dominic Southgate
Abstract: A method of measuring total charge of an insulating layer on a semiconductor substrate includes applying corona charges to the insulating layer and measuring a surface photovoltage of the insulating layer after applying each of the corona charges. The charge density of each of the corona charges is measured with a coulombmeter. A total corona charge required to obtain a surface photovoltage of a predetermined fixed value is determined and used to calculate the total charge of the insulating layer. The fixed value corresponds to either a flatband or midband condition.
Type:
Grant
Filed:
December 26, 2000
Date of Patent:
January 1, 2002
Inventors:
Tom G. Miller, Roger L. Verkuil, Gregory S. Horner
Abstract: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in-situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die-attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.
Type:
Grant
Filed:
October 5, 1998
Date of Patent:
December 11, 2001
Assignee:
Micron Technology, Inc.
Inventors:
Chad A. Cobbley, John VanNortwick, Bret K. Street, Tongbi Jiang
Abstract: A semiconductor wafer has integrated circuit dies formed in an array of rows and columns. Selector circuits occur in the areas between the dies and are electrically connected to the individual dies for selecting between a functional mode and a bypass mode for testing. Probe areas are formed on the periphery of the wafer for accepting probe pins without contacting the bond pads of the dies. The dies and selector circuits are electrically connected to the probe areas for conducting electrical testing of the dies. The testing occurs by selecting only one die in a particular row and column and maintaining the remaining dies in a standby mode.
Abstract: A broadband test procedure detects the onset of stator winding insulation damage, identifies the failure mechanism, determines the winding's susceptibility to further damage, and predicts stator winding failure. This is accomplished by realizing that changes in the stator winding insulation and/or geometry are reflected as changes in the capacitance between the individual windings and, hence, as changes in the stator winding's broadband impedance response. In the currently preferred approach, the impedance response includes the frequency, magnitude, width, and phase of the resonant impedance.
Abstract: Short circuit detection is performed on a plate structure (10) in which a group of first electrical conductors (32) are nominally electrically insulated from, and cross, a group of second electrical conductors (48). In particular, a magnetic current-sensing operation is performed on at least part of the conductors to produce current data indicative of how much, if any, current flows through each of at least part of the conductors. The current data is then examined to determined whether there appears to be a short circuit defect at any location where one of the first conductors crosses one of the second conductors.
Abstract: An arrangement of three plates where the top plate interfaces with the BGA device, the center plate has a structure of channels or openings which is matched with the size and ball pitch of the BGA device that is being handled while the bottom plate interfaces with the tester or target plate. A plurality of center plates is provided to match and equal the plurality of BGA devices that is handled in the BGA testing or BGA semiconductor-manufacturing environment.
Type:
Grant
Filed:
October 30, 1998
Date of Patent:
October 9, 2001
Assignee:
ST Assembly Test Services PTE Ltd
Inventors:
Liop Jin Yap, Wee Boon Tan, Chee-Keong Tan
Abstract: According to the present invention, in a method, two polarized light signals are sent in opposite directions through a sensor exhibiting the Faraday effect. To minimize the influence of light portions that are reflected on light paths, one light signal is transmitted on one wavelength, and the other is transmitted on another wavelength. The present invention is applicable in particularly vibration-compensated magneto-optical current converters for purposes of avoiding the influence of back-reflections on the measuring signal.
Type:
Grant
Filed:
February 14, 2000
Date of Patent:
October 2, 2001
Assignee:
Siemens Aktiengesellschaft
Inventors:
Thomas Bosselmann, Stefan Hain, Michael Willsch
Abstract: An electronic wattmeter is full-floating relative to a source of alternating current (a.c) voltage power that it serves to monitor. It is so full-floating by virtue of a direct current, d.c., power supply that is full floating relative to a.c. ground, and that produces a d.c. voltage that is impressed upon the a.c. voltage, meaning that the d.c. ground is equal to the a.c. voltage. A sense resistor is located in series between the source of a.c. electrical power and an a.c. load. Three resistive voltage dividers respectively between (i) the a.c. voltage at the source side of the sense resistor and a.c. ground, (ii) the a.c. voltage at the source side of the sense resistor and d.c. ground, and (iii) the a.c. voltage at the load side of the sense resistor and d.c. ground, respectively develop at their center taps logic-level, low, (i) first, (ii) second, and (iii) third voltages. The first voltage is indicative of the instantaneous a.c.
Abstract: A single gas tight system which performs multi-functions including reducing the thickness of oxides on contact pads and probing, testing, burn-in, repairing, programming and binning of integrated circuits. A system according to one embodiment of the present invention includes: (a) a gas tight chamber having (1) a plurality of modules each having a holding fixture, a wafer, a probing device, an electronic circuit board, and a temperature control device, (2) a gas source for supplying non-oxidizing gases such as nitrogen and hydrogen into the chamber, (3) a handler for moving the wafers and the probing devices, and (b) a computer coupled to the chamber for controlling and communicating with the handler, the temperature control devices, the holding fixtures and the probing devices. A holding fixture holds a wafer having integrated circuits and aligns the wafer to a probing device.
Abstract: Disclosed is an interposer and test structure for making contact between a substrate and a test bed. One embodiment of the interposer has a floating, rigid conductive element in a nonconductive body which makes temporary contact between the test bed and the substrate. In another embodiment of the invention, the interposer includes two layers of material, in which one layer includes pogo pins for contacting the substrate and the other layer includes pads for contacting the test bed. The pogo pins are on a grid spacing corresponding to that of the substrate input/output pads while the interposer pads are on a grid spacing corresponding to that of the pogo pin contactors of the test bed.
Type:
Grant
Filed:
October 5, 1998
Date of Patent:
August 28, 2001
Assignee:
International Business Machines Corporation
Inventors:
Paul F. Bodenweber, Ralph R. Comulada, Mukta S. Farooq, Charles J. Hendricks, Philo B. Hodge, Vincent P. Peterson, Terence W. Spoor, Kathleen M. Wiley, Yuet-Ying Yu
Abstract: A chuck is provided for holding a semiconductor wafer using a suction force. The chuck includes a chuck plate and may further include a manifold plate, and a seal plate to form a laminated chuck configuration. The chuck plate is disposed about a first axis and includes a first contact region disposed on a first side. The chuck plate further includes a first groove within the first contact region extending generally spirally outwardly from a first location proximate to the first axis to a second location within the first contact region. The chuck plate further includes a first plurality of vacuum holes extending from the first groove into the first side of the chuck plate. A method is provided for a probing a test pad on a semiconductor die disposed on a semiconductor wafer and removing an oxide layer disposed on the test pad. A probe needle contacts the test pad and is overdriven less than or equal to 1 micron into the test pad.
Abstract: Disclosed is a waveform measuring apparatus in which an integration period T can be discretionally set to a value in accordance with the analog voltage cycle of the device being measured with a simple circuit configuration. The waveform measuring apparatus has two integrator circuits for integrating a repeat-cycle analog input with a fixed period. A control portion, consisting of a gate controller and a phase shifter, enables first and second integrators alternatively, such that only one integrator is active at any point in time. The integrals from both integrators are then combined to obtain the integral of the analog input voltage.
Abstract: A wafer of semiconductor material has plural dies formed on the wafer with scribe-line areas of semiconductor material around the each die. Each die includes functional circuitry having input and output bond pads and the dies are arranged adjacent one another in a regular array. Each die includes selectable internal connecting leads connecting the input and output bond pads along one side of the die and the input and output bond pads along an opposite side of the die. External connecting leads are formed on the wafer in the scribe-line areas. The external connecting leads connect input and output bond pads of one die and input and output bond pads of an adjacent die. There is one external lead connecting one bond pad on one die with one corresponding bond pad on the adjacent die.
Abstract: A current determiner having an output at which representations of input currents are provided having an input conductor for the input current and a current sensor supported on a substrate electrically isolated from one another but with the sensor positioned in the magnetic fields arising about the input conductor due to any input currents. The sensor extends along the substrate in a direction primarily perpendicular to the extent of the input conductor and is formed of at least a pair of thin-film ferromagnetic layers separated by a non-magnetic conductive layer. The sensor can be electrically connected to electronic circuitry formed in the substrate including a nonlinearity adaptation circuit to provide representations of the input currents of increased accuracy despite nonlinearities in the current sensor, and can include further current sensors in bridge circuits.
Type:
Grant
Filed:
September 15, 1998
Date of Patent:
June 26, 2001
Assignee:
Nonvolatile Electronics, Incorporated
Inventors:
William C. Black, Jr., Theodore M. Hermann
Abstract: Defects in a patterned substrate are detected by positioning a charged-particle-beam optical column relative to a patterned substrate, the charged-particle imaging system having a field of view (FOV) with a substantially uniform resolution over the FOV; operating the charged-particle-beam optical column to acquire images over multiple subareas of the patterned substrate lying within the FOV by scanning a charged-particle beam over the patterned substrate while maintaining the charged-particle-beam optical column fixed relative to the patterned substrate; and comparing the acquired images to a reference to identify defects in the patterned substrate. The use of a large- FOV imaging system with substantially uniform resolution over the FOV allows acquisition of images over a wide area of the patterned substrate without requiring mechanical stage moves, thereby reducing the time overhead associated with mechanical stage moves. Multiple columns can be ganged together to further improve throughput.
Type:
Grant
Filed:
January 8, 1999
Date of Patent:
June 26, 2001
Assignee:
Schlumberger Technologies, Inc.
Inventors:
Christopher G. Talbot, Chiwoei Wayne Lo
Abstract: A semiconductor testing device is used for testing a semiconductor device which has at least one spherical connection terminal. The testing device includes an insulating substrate having an opening formed therein at a position corresponding to the position of the spherical connection terminal, and a contact member, formed on the insulating substrate, including a connection portion which is connected with the spherical connection terminal, at least the connection portion being deformable and extending into the opening.
Abstract: A probe card, a test method and a test system for testing semiconductor wafers are provided. The test system includes the probe card, a tester for generating test signals, and a wafer prober for placing the wafers and probe card in physical contact. The probe card includes contacts for electrically engaging die contacts on the wafer. The probe card also includes an on board multiplex circuit adapted to fan out and selectively transmit test signals from the tester to the probe card contacts. The multiplex circuit expands tester resources by allowing test signals to be written to multiple dice in parallel. Reading of the dice can be performed in groups up to the limit of the tester resources. In addition to expanding tester resources, the multiplex circuit maintains the individuality of each die, and permits defective dice to be electrically disconnected.
Type:
Grant
Filed:
May 11, 1998
Date of Patent:
June 12, 2001
Assignee:
Micron Technology, Inc.
Inventors:
C. Patrick Doherty, Jorge L. deVarona, Salman Akram