Abstract: A system for testing integrated circuit devices is disclosed in which a tester communicates with a known good device through a channel. Tester-DUT interface circuitry is provided for monitoring the channel while the tester is writing data as part of a test sequence to locations in the known good device. In response, the interface circuitry writes the data to corresponding locations in each of a number of devices under test (DUTs). The interface circuitry monitors the channel while the tester is reading from the locations in the known good device (KGD), and in response performs a comparison between DUT data read from the corresponding locations in the DUTs and expected responses obtained form the KGD.

Abstract: The accuracy of effective channel width extraction in drain current method is improved. There are prepared a transistor with a wide channel width serving as a reference, and a transistor with a narrow channel width that becomes a candidate for extraction (step ST1.1). From the characteristic curve of a plane formed by mask channel width and source-drain conductance, there is extracted a virtual point at which the change of source-drain conductance is estimated to be approximately zero even if the gate overdrive is finely changed. Then, the value of function F is calculated which is defined by the difference between the change of the conductance at the coordinate of the virtual point and the product obtained by multiplying the conductance per unit width by the change of the mask channel width (step ST1.6). From a shift amount (&dgr;) which minimizes the standard deviation of the function F to be obtained (step ST1.

Abstract: A method and system are provided for increasing the accuracy of AC parametric testing. The invention provides a method of precisely estimating signal propagation delay time in an integrated circuit testing apparatus, wherein a plurality of signal propagation delay time measurements are taken and additional delay times are estimated by linearly interpolating the measured delays. A desired test point (desired output voltage at a given time) is established. Using a sample device, a slope is established on a time vs. voltage plot for a line through the desired test point. Where a desired test point falls between strobe times on a tester, linear extrapolation is used to calculate what voltages must be tested for at the two bracketing strobe times in order to guarantee the desired performance at the desired test point. One or more devices are then tested for the calculated voltages at the corresponding bracketing strobe times.

Abstract: A device for testing flat panel displays includes an interface having compliant bumps mounted thereon, which make electrical contact with pads on the display panel. The interface may have a hole formed therein for allowing the passage of light therethrough when the interface is mounted on the display panel. The compliant bumps ensure that all of the bumps make sufficient electrical contact with the pads.

Abstract: There is provided a semiconductor device testing apparatus capable of greatly decreasing an interrupted time of a testing even if a board on which a test pattern supply path and/or a strobe pulse supply path is provided is replaced. A signal propagation delay time of the test pattern supply path through which a test pattern signal is supplied to a semiconductor device under test and a signal propagation delay time of the strobe pulse supply path through which a strobe pulse is supplied to a signal read circuit reading therein a logical value of a response signal outputted from the semiconductor device under test are measured respectively, and differences between the measured respective values and predetermined corresponding delay times are found respectively. The obtained time differences are stored as delay correcting data in a non-volatile memory or corresponding non-volatile memories.

Abstract: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in-situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die-attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.

Abstract: Virtual device fixturing is used to test transistor products, such as LDMOS power amplifier products, in the final packaging and testing stage of device fabrication. The input and output impedance transformation networks of a typical test fixture are implemented in software. The impedance matching function, normally performed by the physical input and output impedance transformation networks of the fixture, is supplanted by de-embedded scatter parameter calibration files. Test equipment, such as a vector network analyzer, attaches to a universal test fixture, while the software scatter parameter components are responsible for making the calibrations necessary to present the device under test with a matching low impedance.

Abstract: An IC to be tested having solder bumps is mounted on an IC socket mounted on a test board. The IC socket is provided with a contact unit including a plurality of straight contact pins each having an lower end connected to the test board and an upper end connected to the solder bumps and also including an elastic member for supporting the plurality of contact pins. A diameter of the plurality of contact pins is configured to be sufficiently small for the plurality of contact pins to pierce the respective solder bumps so that an electrical connection is established by the upper end of each of the plurality of solder bumps piercing an associated one of the solder bumps.

Abstract: A method and apparatus for handling small semiconductor devices in the testing of these devices. Multiple devices are mounted within a device strip carrier and are positioned in the testing position. This positioning of the device strip carriers is performed using device strip carrier alignment tools; the device strip carrier can readily be repositioned with respect to the test head/probe card for testing of multiple devices contained within the device strip carrier.

Abstract: An improved inner component board arrangement and corresponding assembly for an electric utility meter is disclosed The enhanced structure offers comprehensive stability and protection of circuit boards and corresponding electronic components within an integrated meter assembly. The arrangement generally includes at least two printed circuit boards housed in a casing structure. Various projections extend from the casing structure to effectively position and secure the printed circuit boards within an overall component assembly, Specific projections employed for positioning the circuit boards include tapered locator pins and respective mating holes as well as key projections that interconnect with slots located in selected circuit boards. Snaps project from casing components to securely constrain the circuit boards within the component assembly. Established orientation of various components and projections significantly facilitates the meter assembly process.

Abstract: Defects in a patterned substrate are detected by positioning a charged-particle-beam optical column relative to a patterned substrate, the charged-particle imaging system having a field of view (FOV) with a substantially uniform resolution over the FOV; operating the charged-particle-beam optical column to acquire images over multiple subareas of the patterned substrate lying within the FOV by scanning a charged-particle beam over the patterned substrate while maintaining the charged-particle-beam optical column fixed relative to the patterned substrate; and comparing the acquired images to a reference to identify defects in the patterned substrate. The use of a large-FOV imaging system with substantially uniform resolution over the FOV allows acquisition of images over a wide area of the patterned substrate without requiring mechanical stage moves, thereby reducing the time overhead associated with mechanical stage moves. Multiple columns can be ganged together to further improve throughput.

Abstract: A reconfigurable and customizable nest for a device under test. The reconfigurable nest includes a non-metallic nest plate and nesting blocks. The nesting blocks are positioned around the device under test using removable toolless fastening elements such as double-stick tape. Using the removable toolless fastening elements, the nest may be reconfigured for different devices under test.

Abstract: The invention relates to a test device for testing electronic components mounted on a carrier such as a lead frame, comprising: a transport path for supplying a carrier for testing; a manipulator for engaging and displacing a supplied carrier; a test contact with which a carrier and/or at least one component mounted on the carrier can be placed in contact by the manipulator; and a transport path for discharging a tested carrier. The invention also embraces a test assembly which includes at least one described test device. The invention furthermore provides a method for testing electronic components mounted on a carrier and method for calibrating a test device.

Abstract: Disclosed is an improved probe housing mechanism that will allow for the quick release of a probe tip from a testing tool. The invention includes a probe housing, a double cantilevered beam for holding a probe tip, and a releasable spring mechanism for holding the beam into place. The spring mechanism can be released by squeezing the spring together or by releasing a non-removable locking screw, thereby allowing the beam to be slidably removed from the probe housing for easy replacement.

Abstract: A contact device having a plurality of nominally coplanar first contact elements makes electrical contact with corresponding nominally coplanar second contact elements of an electronic device when the contact device and the electronic device are positioned so that the plane of the first contact elements is substantially parallel to the plane of the second contact elements and relative displacement of the devices is effected in a direction substantially perpendicular to the plane of the first contact elements and the plane of the second contact elements. The contact device comprises a stiff substrate having a major portion with fingers projecting therefrom in cantilever fashion, each finger having a proximal end at which it is connected to the major portion of the substrate and an opposite distal end and there being one or two contact elements on the distal end of each finger. It is necessary to effect relative displacement of the devices by a distance d from first touchdown to achieve last touchdown.

Abstract: The invention relates to an adapter base for receiving electronic test objects (DLTT) comprising an outer group (array) of contact pins (26) that pass through the base from the upper side to the lower side, as well as an inner matrix (38) that consists of contacts (36) that protrude only on the lower side corresponding to an area (28) on the upper side which presents no contacts. Each contact pin (26) is connected to a series connection (30) embodied in the adaptor (24) and constituted by a switching transistor (32), as well as at least one capacitor (34) that via a control signal can be connected and disconnected by means of the gate (G) of the switching transistor (32), the gate being connected to a corresponding contact (36) on the lower side.

Abstract: A broadband test procedure detects the onset of stator winding insulation damage, identifies the failure mechanism, determines the winding's susceptibility to further damage, and predicts stator winding failure. This is accomplished by realizing that changes in the stator winding insulation and/or geometry are reflected as changes in the capacitance between the individual windings and, hence, as changes in the stator winding's broadband impedance response. In the currently preferred approach, the impedance response includes the frequency, magnitude, width, and phase of the resonant impedance.

Abstract: There is provided a semiconductor device testing apparatus capable of greatly decreasing an interrupted time of a testing even if a board on which a test pattern supply path and/or a strobe pulse supply path is provided is replaced. A signal propagation delay time of the test pattern supply path through which a test pattern signal is supplied to a semiconductor device under test and a signal propagation delay time of the strobe pulse supply path through which a strobe pulse is supplied to a signal read circuit reading therein a logical value of a response signal outputted from the semiconductor device under test are measured respectively, and differences between the measured respective values and predetermined corresponding delay times are found respectively. The obtained time differences are stored as delay correcting data in a non-volatile memory or corresponding non-volatile memories.

Abstract: A programmable voltage divider has normal and test modes of operation. The divider includes first and second supply nodes, a divider node that provides a data value, and a first divider element that is coupled between the first supply node and the divider node. The divider also includes a controlled node, a second divider element that has a selectable resistivity and that is coupled between the divider node and the controlled node, and a test circuit that is coupled between the controlled node and the second supply node. During the normal mode of operation, the first and second divider elements generate the data value having a first logic level when the second divider element has a first resistivity, and generate the data value having a second logic level when the second divider element has a second resistivity. The test circuit generates a first voltage at the controlled node during the normal mode of operation, and generates a second voltage at the controlled node during the test mode of operation.

Abstract: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in-situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die-attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection bumps on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of “known good dice” (KGD) rework procedures during repair is eliminated.