Abstract: Characterization of free-space electromagnetic energy pulses (15) using a chirped optical probe beam is provided. An electro-optic or magneto-optic crystal (14) is positioned such that the free-space radiation and chirped optical probe signal co-propagate, preferably in a co-linear common direction, through the crystal where a temporal waveform of the free-space radiation is linearly encoded onto a wavelength spectrum of the chirped optical probe signal. The temporal waveform of the free-space radiation is then reconstructed using, for example, a dynamic subtraction of the spectral distribution of the chirped optical probe signal without modulation from the spectral distribution of the chirped optical probe signal with modulation by the free-space radiation.

Abstract: A method for testing unpackaged semiconductor dice having raised contact locations (e.g., bumped bond pads) and a method for forming an interconnect suitable for testing this type of dice are provided. The interconnect includes a substrate having contact members comprising an array of sharpened elongated projections. The sharpened projections are formed by etching (or by growing and removing an oxide) through exposed areas of a mask. A conductive layer is formed on the sharpened projections and is in electrical communication with conductive traces formed on the substrate. The conductive layer can be formed as a layer of metal, as a stack of metals including a barrier metal, as a silicide, or as a layer of polysilicon. For testing an unpackaged die, the interconnect and die are placed in a temporary carrier and biased together.

Abstract: A a testing circuit for a semiconductor device comprising a plurality of external terminals; a plurality of external terminal wires, each of which is connected to one of the external terminals; a testing external terminal; a testing wire connected to the testing external terminal; a plurality of switches placed between the testing wire and the external terminal wires; and a control circuit for selecting one of the switches to bring it into conduct, in response to a test signal. Connection states of power and GND terminals can be conveniently tested and a highly reliable semiconductor device can be provided.

Abstract: A probe assembly consisting of a servo mechanism or actuator providing multi-direction motion; a probe mounting attached to the actuator; and pin probes attached to the probe mounting making an electrical connection to pins of a device or package under test. The pin probe includes a shaft terminating in an end section having a conical shaped recessed area. The conical feature contained in the probe allows the probe to contact a pin or array of pins that are less then ideally located, but within their geometrical tolerance. The probe assembly thus constructed, provides reliable test measurements. It also increases test throughout by minimizing test setup time when the DUT has misaligned or bent pins. The setup can be used on a manual probe station, or in a mass production bed of nails type tester. The assembly can also be in the form of a gang probe wherein pin probes are arranged in a bed of nails arrangement to make contact with all the pins of the DUT simultaneously.

Abstract: A test fixture for electrically connecting a limited-access test target on a loaded circuit board with an interface probe of a tester may comprise an elongate test probe having a first end and a second end and a probe-mounting plate having a first side and a second side. The first end of the elongate test probe is substantially aligned with the limited-access target on the loaded circuit board when the test fixture is positioned adjacent the loaded circuit board. A larger-pitch target on the first side of the probe-mounting plate is substantially aligned with the elongate test probe so that the larger-pitch target contacts the second end of the elongate test probe. A personality pin having a first end and a second end is mounted to the second side of the probe-mounting plate. The personality pin contacts the interface probe of the tester when the test fixture is mounted on the tester. A first end of an elongate wire is attached to the larger-pitch target.

Abstract: A method and apparatus for handling small semiconductor devices in the testing of these devices. Multiple devices are mounted within a device strip carrier and are positioned in the testing position. This positioning of the device strip carriers is performed using device strip carrier alignment tools; the device strip carrier can readily be repositioned with respect to the test head/probe card for testing of multiple devices contained within the device strip carrier.

Abstract: A testing station tests integrated circuits and determines if the integrated circuits pass or fail predefined tests. The integrated circuits are placed in a pass bin if the integrated circuits passed the tests, or a fail bin if the integrated circuits failed the tests. A marking station marks identification information on the integrated circuits in the pass bin. The testing and marking stations are both included in a single, integrated tester-marker system.

Abstract: An external spring probe is provided having a first section and a second section which extend and compress relative to each other. The first section consists of a tip at one end and a first contact component opposite the tip. A flange extends radially outward between the tip and the first contact component. The second section consists of a tip at one end and a second contact component opposite the tip. The second contact tip is in contact with the first contact tip. A flange extends radially outward between the second section tip and the second contact component. A spring is sandwiched between the two flanges surrounding the two contact components. The first and second contact components remain in contact with each other during compression and extension of the two sections.

Abstract: A method of engaging electrically conductive test pads on a semiconductor substrate having integrated circuitry for operability testing thereof includes: a) providing an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate; b) engaging the grouping of apexes with the single test pad on the semiconductor substrate; and c) sending an electric signal between the grouping of apexes and test pad to evaluate operability of integrated circuitry on the semiconductor substrate. Constructions and methods are disclosed for forming testing apparatus comprising an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate.

Abstract: A triggered integrated circuit (IC) tester in accordance with the invention organizes a test of an IC into a succession of test cycles. A vector generated prior to the start of each test cycle references the test activities to be carried out during the test cycle. The tester generates a set of N periodic timing signals, T0 through T(N−1), each having a period equal to the duration of one test cycle with the timing signals being distributed in phase so that their edges evenly divide each test cycle into N intervals. Each test cycle nominally starts on an edge of the T0 signal, and each vector referencing a test event also indicates a nominal time delay following the start of the test cycle at which the event is to occur by referencing one of the timing signals T0 through T(N−1). However whenever the tester receives an input trigger signal edge, it determines an offset between the most recent T0 signal edge and the occurrence of the trigger signal edge.

Abstract: A spring element used in a temporary package for testing semiconductors is provided. The spring element is compressed so as to press the semiconductor, either in the form of a bare semiconductor die or as part of a package, against an interconnect structure. The spring element is configured so that it provides sufficient pressure to keep the contacts on the semiconductor in electrical contact with the interconnect structure. Material is added and/or removed from the spring element so that it has the desired modulus of elasticity. The shape of the spring element may also be varied to change the modulus of elasticity, the spring constant, and the force transfer capabilities of the spring element.

Abstract: An ice detector includes a pair of electrodes connected by a pair of leads to a control unit which measures the admittance between leads to thereby sense and detect the presence of ice and other contaminants formed on top thereof utilizing a detection circuit. The electrodes are integrated into patch which can be placed at different locations on an aircraft.

Abstract: A power supply applies a power supply voltage to a large number of devices formed on a wafer W. In the state where the devices are quiescent, the quiescent power supply currents flowing through them are measured. If measurements are greater than a setting value, the corresponding devices are determined to be defective. A cutoff circuit prevents voltage application to such defective devices. After this preliminary test, an IDDQ test, an AC test, a DC test and a function test are executed. These tests are executed not by a control station but by an application/measurement module provided for a prober.

Abstract: An integrated circuit (IC) tester employs a pattern generator including an instruction processor executing an algorithmic program stored in a program memory. The program defines a sequence of vectors defining test activities to be carried out during successive cycles of a test on an IC. In the course of executing the program, the instruction processor stores in various registers and counters “program status” data that the processor uses to keep track of program execution. The status data may include, for example, the current program memory address, loop and repeat counts, return addresses and the like. The pattern generator also includes a random access “program status” memory for storing a selected portion of the program status data at selected points during a test.

Abstract: A method of engaging electrically conductive test pads on a semiconductor substrate having integrated circuitry for operability testing thereof includes: a) providing an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate; b) engaging the grouping of apexes with the single test pad on the semiconductor substrate; and c) sending an electric signal between the grouping of apexes and test pad to evaluate operability of integrated circuitry on the semiconductor substrate. Constructions and methods are disclosed for forming testing apparatus comprising an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate.

Abstract: The accuracy of effective channel width extraction in drain current method is improved. There are prepared a transistor with a wide channel width serving as a reference, and a transistor with a narrow channel width that becomes a candidate for extraction (step ST1.1). From the characteristic curve of a plane formed by mask channel width and source-drain conductance, there is extracted a virtual point at which the change of source-drain conductance is estimated to be approximately zero even if the gate overdrive is finely changed. Then, the value of function F is calculated which is defined by the difference between the change of the conductance at the coordinate of the virtual point and the product obtained by multiplying the conductance per unit width by the change of the mask channel width (step ST1.6). From a shift amount (&dgr;) which minimizes the standard deviation of the function F to be obtained (step ST1.

Abstract: An insert is provided for testing a chip-scale-packaged microelectronic device having an encapsulant-protrusion and a ball-grid-array of outwardly-projecting contacts. The insert comprises a substrate of mono-crystalline silicon. Walls of the substrate define a plurality of pockets that are configured to receive and contact the outwardly-projecting contacts of the microelectronic device. Additional walls of the substrate define a recess disposed amongst the plurality of pockets. The recess has a width greater than the widths of any of the pockets. Additionally, the recess comprises a perimeter greater than that of the encapsulant-protrusion of the chip-scale-packaged microelectronic device, and a depth operative to clear the encapsulant-protrusion when the chip-scale package is seated upon the insert.

Abstract: A board inspection probe for inspecting pattern lines on a circuit board for defects in a non-contact manner. The probe has an electrode for radiating an electrical signal or receiving an electrical signal radiated from a first pattern line. The probe also has a shield to prevent, from reaching the electrode, unwanted radiant waves emitted from pattern lines located in a region except a board region immediately below an electrode surface of the electrode. This shield is terminates near the electrode surface of the electrode, so that radiant waves from only pattern lines located on the board region immediately below the electrode are received.

Abstract: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in-situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die-attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.

Abstract: An electronic probe has a termination portion, a filter, and an impedance device. The termination portion is connected between a transmission line end and a common node. The termination portion has a termination resistor and a termination capacitor connected in series between the transmission line end and the common node. The filter has a resistor connected in parallel with a capacitor and an inductor connected in series with the filter resistor and filter capacitor combination. The components are connected between the transmission line end and an output. An impedance device is connected between the output and the common node. A zero is associated with the termination portion and a pole is associated with the filter. The frequency of the zero is approximately equal to the frequency of the pole. The probe provides a device for measuring tri-state logic circuits without overloading the circuits.