Abstract: Systems and methods for performing backup operations and other secondary copy operations for mail servers, such as Exchange servers, are described. In some cases, the systems and methods perform multi-streaming backup and other copy operations using a single mailbox agent, which launches backup streams via a coordinator that determines when to launch streams, at what mailboxes (or folders) to launch the streams, and so on. The coordinator communicates with controllers at different machines (e.g., servers) to be backed up, and may assign streams, mailboxes, and so on, to the different controllers, which perform the backup operations for their assigned mailboxes and/or clients.

Abstract: Systems and methods for providing and/or facilitating live browsing of granular mail or mailbox data, such as data stored within Exchange mailboxes, are described. For example, the systems and methods may provide mechanisms for browsing and/or restoring granular data (e.g., email data) from an Exchange database backup copy (or other secondary copy), without having to restore the entire database from the backup copy.

Abstract: A method including: receiving, via a processor, established upper bounds for dynamic structures in a multi-tenant system; creating, via the processor, arrays comprising related memory-management unit (MMU) mappings to be placed together; and placing the dynamic structures within the arrays, the placing comprising for each array: skipping an element of the array based on determining that placing a dynamic structure in that element would cause the array to become overcommitted and result in a layout where accessing all elements would impose a translation look aside buffer (TLB) replacement action; and scanning for an array-start entry by placing the start of a first element at an address from which an entire array can be placed without TLB contention, and accessing, via the processors, all non-skipped elements without incurring TLB replacements.

Abstract: An apparatus, system, and method are disclosed for efficiently managing commands in a solid-state storage device that includes a solid-state storage arranged in two or more banks. Each bank is separately accessible and includes two or more solid-state storage elements accessed in parallel by a storage input/output bus. The solid-state storage includes solid-state, non-volatile memory. The solid-state storage device includes a bank interleave that directs one or more commands to two or more queues, where the one or more commands are separated by command type into the queues. Each bank includes a set of queues in the bank interleave controller. Each set of queues includes a queue for each command type. The bank interleave controller coordinates among the banks execution of the commands stored in the queues, where a command of a first type executes on one bank while a command of a second type executes on a second bank.

Abstract: A processor includes a translation lookaside buffer (TLB) to store a TLB entry, wherein the TLB entry comprises a first set of valid bits to identify if the first TLB entry corresponds to a virtual address from a memory access request, wherein the valid bits are set based on a first page size associated with the TLB entry from a first set of different page sizes assigned to a first probe group; and a control circuit to probe the TLB for each page size of the first set of different page sizes assigned to the first probe group in a single probe cycle to determine if the TLB entry corresponds to the virtual address from the memory access request.

Abstract: The present disclosure includes apparatuses and methods for logical to physical mapping. A number of embodiments include a logical to physical (L2P) update table, a L2P table cache, and a controller. The controller may be configured to cause a list of updates to be applied to an L2P table to be stored in the L2P update table.

Abstract: The present disclosure includes memory blocks erasable in a single level cell mode. A number of embodiments include a memory comprising a plurality of mixed mode blocks and a controller. The controller may be configured to identify a particular mixed mode block for an erase operation and, responsive to a determined intent to subsequently write the particular mixed mode block in a single level cell (SLC) mode, perform the erase operation in the SLC mode.

Abstract: A data storage apparatus in accordance with an embodiment may include a memory device, a memory controller, and a media controller. The memory device may store data. The memory controller may output a packetized request signal for the memory device and receive a response signal to the packetized request signal according to a predetermined protocol. In response to a request packet provided from the memory controller, the media controller may generate a media command corresponding to the memory device, perform a read or write operation on the memory device, generate a response packet upon completion of the read or write operation, and transmit the generated response packet to the memory controller.

Abstract: Methods, systems, and devices for refresh command management are described. A memory device may conduct a refresh operation to preserve the integrity of data stored to one or more memory cells. In some examples, the frequency of refresh operations conducted may be based on the memory device's temperature and may be initiated based on one or more commands received from an external device (e.g., a host device). Each command may be transmitted by the host device at a defined rate, which may impact the rate at which the memory device conducts one or more refresh operations. The memory device may postpone or skip at least a portion of one or more refresh operations based on one or more operating parameters of the memory device.

Abstract: A memory card is attached to a host device, and includes a data control circuit which transfers data with respect to the host device in synchronism with a rise edge and a fall edge of a clock signal.

Abstract: A memory system includes: a memory device storing host data provided from a host; and a memory controller managing and transferring the host data between the host and the memory device, wherein the memory controller comprises: a write buffer temporarily storing the host data to be transferred to the memory device; a buffer monitoring device checking a usage amount of the write buffer during a predetermined period; a buffer usage comparing device generating a flush control signal based on a usage amount comparison result by comparing the usage amount checked during a current period corresponding to the predetermined period with the usage amount checked during a previous period corresponding to the predetermined period; and a first flush device transferring the host data temporarily stored in the write buffer to the memory device in response to the flush control signal.

Abstract: A module manages memory in a computer. The module monitors usage of a primary memory associated with the computer. The primary memory stores memory blocks in a ready state. In response to primary memory usage by the memory blocks in the ready state exceeding a ready state threshold, the module compresses at least some of the memory blocks in the ready state to form memory blocks in a ready and compressed state. In response to primary memory usage by the memory blocks in the ready and compressed state exceeding a release threshold, the module releases at least some of the memory blocks in the ready and compressed state. In response to primary memory usage by the memory blocks in the compressed state exceeding a compressed threshold, the module transfers at least some memory blocks in the compressed state to a secondary memory associated with the computer.

Abstract: A memory system and an operating method thereof are provided. The memory system includes a buffer memory storing a plurality of meta-slices constituting meta-data, and a memory controller marking meta-slices being updated, among the plurality of meta-slices stored in the buffer memory, as dirty meta-slices, generating journal data including update information corresponding to the dirty meta-slices, and flushing the journal data together with one of the dirty meta-slices to a non-volatile memory device.

Abstract: A semiconductor device, memory system, and method are provided. One example of the semiconductor device is disclosed to include a host interface that enables bi-directional communications with a host computer, a processor subsystem that enables processing of read or write requests received at the host interface, and one or more storage media interfaces, each of the one or more storage media interfaces being convertible between a first configuration and a second configuration, where the first configuration of a storage media interface enables a direct connection with a computer memory device, and where the second configuration of the storage media interface enables a connection with a plurality of computer memory devices via an expander and/or re-timer.

Abstract: A memory device may comprise circuitry to adjust between latency and throughput in transferring information through a memory port, wherein the circuitry may be capable of configuring individual partitions or individual sectors as high-throughput storage or low-latency storage.

Abstract: An illegal address access blocking circuit includes a first register and a second register to set upper and lower limit values of an address range within which access to an external device is allowed. A first comparator compares a first value and the upper limit value, and outputs a high level signal when the first value is larger than the upper limit value. A second comparator compares the first value and the lower limit value, and outputs a low level signal. A first and logic circuit holds a logic sum of the high and low level signals, and outputs the logic sum as a third output, and a second logic circuit compares a fourth value inputted to a first request control line and the third output, and outputs a result of the comparison to a second request control line.

Abstract: A multi-chip package, a controlling method of the multi-chip package and a security chip are provided. The multi-chip package includes a memory chip and a security chip. The security chip is coupled between the memory chip and a host. The security chip includes a processing circuit. The processing circuit is for enabling a security path to input an input-output signal into the processing circuit for executing a security procedure and accessing the memory chip, if a command is received by the processing circuit and the command includes a security requirement.

Abstract: Compressibility instrumented dynamic volume provisioning is disclosed. For example, a plurality of storage pools includes first and second storage pools, and is managed by a storage controller that receives a request to provision a first persistent storage volume associated with a first container, where the first storage pool has a first storage configuration including a deduplication setting, a compression setting, and/or an encryption setting. The first persistent storage volume is created in the first storage pool based on a first storage mode stored in metadata associated with the first container, where the storage mode includes a deduplication mode, a compression mode, and/or an encryption mode. A second persistent storage volume is in the second storage pool with a second storage configuration different from the first storage configuration based on a second storage mode associated with a second container.

Abstract: A computer-implemented method according to one embodiment includes identifying data stored within a first virtual storage tier of a storage system, analyzing one or more characteristics of the data, and conditionally transferring the data from the first virtual storage tier of the storage system to a second virtual storage tier of the storage system, based on the analyzing.

Abstract: A semiconductor system may include: a volatile memory device that stores an address mapping table including mapping information for a non-volatile memory device; and a control device suitable for reading one or more seed values from the volatile memory device before the address mapping table is stored, generating a plurality of random values based on the seed values, and initializing mapping information to the plurality of random values.