Abstract: An apparatus may include a first connector having at least a first host communication path for connection to a host device, a second connector that physically alters at least a first signal path in response to a physical connection at the second connector, and a controller section that communicates a first set of configuration information over the first host communication path when the first signal path is in an unaltered state, and a second set of configuration information when the first signal path is in an altered state.

Abstract: An information processing apparatus switches from a regular power mode to a power saving mode in the event that a first control unit does not process packets for a certain period of time. The information processing apparatus includes a packet table in which packets to be processed by the first control unit are registered, and a determining unit for determining whether the system of the information processing apparatus can switch to the power saving mode. In the event that the determining unit determines that the system can switch to the power saving mode, a network controller processes the packets based on the packet table.

Abstract: In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn via one or more physical units to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed.

Abstract: A device for providing a plurality of clock signals from a common clock signal. The device includes an input for receiving the common clock signal, a first clock signal path for providing a first output clock signal on the basis of the common clock signal and a second clock signal path for providing a second output clock signal. The second clock signal path includes a clock processing device for changing a phase of the common clock signal to provide the second clock signal.

Abstract: A device comprising a temperature measurement module, a performance state module, and a fan speed module. The temperature measurement module is configured to determine a temperature in a server, and to output a first control signal when temperature in the server is above a threshold. The performance state module is configured to change a performance state of the device to a lowest system performance state in response to the first control signal, and further configured to reduce a processor power consumption and a subsystem power consumption to a minimum power level in response to reducing the performance state to the lowest system performance state. The fan speed module is configured to reduce a fan speed to a minimum fan speed level based on the first control signal.

Abstract: Techniques and systems are provided that work to minimize the energy usage of computing devices by building and using models that predict the future work required of one or more components of a computing system, based on observations, and using such forecasts in a decision analysis that weighs the costs and benefits of transitioning components to a lower power and performance state. Predictive models can be generated by machine learning methods from libraries of data collected about the future performance requirements on components, given current and recent observations. The models may be used to predict in an ongoing manner the future performance requirements of a computing device from cues. In various aspects, models that predict performance requirements that take into consideration the latency preferences and tolerances of users are used in cost-benefit analyses that guide powering decisions.

Abstract: A power delivery technique which involves connecting power sourcing equipment (PSE) with a powered device (PD) through data communications cabling (e.g., an Ethernet cable). The technique further involves negotiating an acceptable power level for the PD and a data rate for the PD, and enforcing delivery of power to the PD using only wire pairs of the data communications cabling which carry data between the PSE and the PD. As a result, the PSE does not deliver any power to the PD through wire pairs which are not data-active.

Abstract: Systems and methods for performing output delay adjustment are provided for application in serial-connected devices operating as slave devices. A master device provides a clock to the first slave device, and each slave device passes the clock to the next slave device in turn, and the last slave device returns the clock to the master device. The master device compares the outgoing clock to the returned clock and determines if an output delay adjustment is needed. If so, the master device generates and outputs commands for the slave devices to perform output delay adjustment. The slave devices apply the output delay to the clock signal, but may also apply the delay to other output signals. Each of the slave devices has a circuit for performing output delay adjustment. In some implementations, each slave device is a memory device, and the master device is a memory controller.

Abstract: In a packet processing device capable of reducing power consumption when time intervals between input packets is increased and an input traffic capacity is reduced, packet processors, N in number (N is an integer of one or more), sequentially perform processing in response to an input packet to output a processed packet and processor packet detectors detect whether or not a packet exists in the packet processors. Responsive to a result of the processor packet detectors, a power supply switch unit controls power supply to the packet processors. Thus, each of the packet processors is intermittently put into an active state by intermittent power supply.

Abstract: The asynchronous circuit insensitive to delays comprises at least one time delay insertion circuit on the propagation path of a signal. The delay insertion circuit comprises, between an input and an output of the signal, a Muller C-element and a plurality of delay circuits connected in series to an output of the Muller C-element. The outputs of the delay circuits are connected to corresponding inputs of a multiplexing circuit having an output constituting the output of the delay insertion circuit. The Muller C-element comprises an input connected to the output of the last delay circuit via an inverter gate, and an input constituting the input of the signal to the delay insertion circuit. The multiplexing circuit control circuit preferably comprises a random generator.

Abstract: Systems and methods according to these exemplary embodiments provide for optimizing voltage use in digital circuits. This can be obtained by creating situations for digital circuits such that the effective critical path (ECP) can be used such as, for example, the case where a digital circuit includes a plurality of voltage domains powered by individual and possibly different voltage sources. This can then reduce voltage use in digital circuits.

Abstract: Provided is a low power consumption processor. The processor includes: a plurality of blocks; a memory storing instructions that control each of the plurality of blocks; and a multi power controller generates a signal that activates at least one of the plurality of blocks according to an address storing the instruction, and provides a normal power voltage or a reduction power voltage in response to the activation signal.

Abstract: A computer system has a central processing unit, a north bridge electrically connected to the central processing unit, memory electrically connected to the north bridge, a south bridge electrically connected to the north bridge, and a peripheral device electrically connected to the south bridge. The south bridge includes a register for storings a plurality of pre-fetched read data to provide the pre-fetched read data to the peripheral device. The north bridge has an address queue module for storing an address of the pre-fetched read data, and a snooping module for checking whether a data value corresponding to the address is updated by the CPU. The north bridge assists the south bridge in obtaining and maintaining the pre-fetched read data for high efficiency and accuracy of read caching of the south bridge.

Abstract: Systems and methods for correcting clock duty cycle are provided for application in serial-connected devices operating as slave devices. A master device provides a clock to the first slave device, and each slave device passes the clock to the next slave device in turn, and the last slave device returns the clock to the master device. The master device compares the outgoing clock to the returned clock and determines if a duty cycle correction is needed. If so, the master device generates and outputs commands for the slave devices to perform duty cycle adjustment. Each of the slave devices has a circuit for performing duty cycle adjustment. In some implementations, each slave device is a memory device, and the master device is a memory controller.

Abstract: A power controller for a peripheral bus interface. A peripheral bus power controller includes a first terminal, a second terminal coupled to receive an power enable input signal from a host controller, and a third terminal coupled to provide an over-current output signal indicative of an over-current condition to the host controller. The peripheral bus power controller further includes an enable circuit configured to assert a power enable output signal on the first terminal responsive to receiving the power enable input signal and a first buffer configured to provide the over-current output signal to the host controller responsive to the power controller detecting the over-current condition on the first terminal.

Abstract: A data control unit includes a primary power supply line to which a primary power supply voltage is supplied; a secondary power source line to which a secondary power supply voltage is supplied; a voltage converter for converting the primary power supply voltage into the secondary power supply voltage; a voltage level detection unit which is connected to the primary power source line, and outputs a voltage level detection signal; a reset signal generator which is connected to the secondary power source line, and outputs a reset signal; and a control signal generation unit which receives the voltage level detection signal and the reset signal, and outputs a control signal. The data control unit detects power supply cutoff, and secures the time for sufficient backup process.

Abstract: A power manager of an information handling system selectively commands a first or second source voltage from an AC-to-DC adapter based upon power consumption of the information handling system. A lower direct current voltage is provided during reduced power consumption so that DC-to-DC conversion in a power supply is more efficient. A higher direct current voltage is provided during increased power consumption so that the current required to provide the increased power remains below a threshold current, thus allowing the power system to have components that operate at lower current levels under high power consumption operations yet with increased efficiency during low power consumption operations.

Abstract: A data processing system supporting one or more virtual processing apparatuses is provided with external interrupt interface hardware 26 and virtual interface hardware 28. Hypervisor software responds to an interrupt received by the external interrupt interface hardware 26 to write data characterising that interrupt into list registers 18 of the virtual interface hardware 28. A guest operating system for the virtual machine of the virtual data processing apparatus being emulated may then read data from the virtual interface hardware 28 characterising the interrupt to be processed by that virtual machine. The virtual machine and the guest operating system interact with the virtual interface hardware 28 as if it were external interface hardware. The hypervisor software is responsible for maintaining the data within the virtual interface hardware 28 to properly reflect queued interrupts as received by the external interface 26.

Abstract: There is provided a storage system including a file server connecting to a computer over a network and a storage apparatus connecting to the file server connecting over the network, wherein the file server includes a first controller, the storage apparatus includes multiple storage devices having multiple storage areas and a second controller that controls accesses to the multiple storage areas, each of the multiple storage areas has at least one power saving mode among multiple power saving modes with different shift times from the power saving modes to a ready mode, the first controller, in response to the reception of data from the computer, sets an indicator relating to the performance of response to an access from the computer to the data and refers to the indicator of the data and selects a first storage area having the power saving mode satisfying the indicator, and the second controller stores the data to the first storage area.