Abstract: An embodiment of a multichip module is disclosed. For this embodiment of the multichip module, a transceiver die has transceivers. A crossbar switch die has at least one crossbar switch. A protocol logic blocks die has protocol logic blocks. The transceiver die, the crossbar switch die, and the protocol logic blocks die are all coupled to an interposer. The interposer interconnects the transceivers and the protocol logic blocks to one another and interconnects the protocol logic blocks and the at least one crossbar switch to one another.

Abstract: Present techniques involve systems and methods for driving a synchronous bus by implementing repeaters along the bus to restore and/or amplify a signal transmitted through the bus. In one embodiment, a repeater may be implemented at different sections of a synchronous bus, and each repeater may be activated according to where a signal is to be transmitted. In another embodiment, decoders may be configured to each repeater on the synchronous bus. As a signal directed to a section of a bus is transmitted through the bus, each sequential decoder may identify the bus section to which a signal is directed. The decoder may enable its corresponding repeater based on the bus section to which the signal is directed, such that all repeaters along the bus which come before the signal destination may be enabled to allow signal transmission through the bus and signal restoration by the repeaters.

Abstract: A method and apparatus for dynamically controlling a cache size is disclosed. In one embodiment, a method includes changing an operating point of a processor from a first operating point to a second operating point, and selectively removing power from one or more ways of a cache memory responsive to changing the operating point. The method further includes processing one or more instructions in the processor subsequent to removing power from the one or more ways of the cache memory, wherein said processing includes accessing one or more ways of the cache memory from which power was not removed.

Abstract: In some embodiments, provided is a way for devices to request S0ix (or the like) entry and exit.

Abstract: A storage assembly includes a physical expander for connection in use to two or more SCSI initiators, and two or more storage devices, wherein the expander is controlled such that it presents plural virtual expanders. A method for connecting two or more storage devices to two or more SCSI initiators within a storage assembly, includes providing a physical expander for connection in use to the two or more SCSI initiators, and two or more storage devices, and controlling the single expander such that it presents plural virtual expanders.

Abstract: A method includes receiving data intended for a destination and sending a power flit to the destination via a route. The power flit wakes at least one component on the route. The method also includes sending the data as a data flit to the destination via the route after sending the power flit. The power flit can include a header indicating the destination and a source of the received data. The power flit can be formed by extracting destination data from the received data.

Abstract: A computer system is provided with an event counter, a CPU, a memory, an external device, a hub M31 and a hub I33. The computer system is further provided with a clock change module 50. System software 60 and applications 70a to 70m operate, and the clock change module 50 specifies a clock with which the applications 70 are executed. Based on stall cycles read from the event counter 21, the clock change module 50 specifies the clock that maximizes performance or power consumption characteristic while satisfying execution constraint 90.

Abstract: Provided is a conveyance control system in which fast and smooth control is realized without causing a control delay by a processing delay of a control apparatus such as a PLC, and wiring between a control object and a central control unit is omitted. A conveyance control system according to the present invention includes a plurality of data processing slave stations connected through a common transmission line. The data processing slave station obtains information about a predetermined station from monitor/control data about a plurality of stations of the data processing slave station transmitted to the common transmission line, determines and adjusts control/monitoring of an own station and outputs information about an own station to the common transmission line. The information about an own station output to the common transmission line from the data processing slave station is obtained by a different station as part of the monitor/control data to become a control/monitor factor of the different station.

Abstract: A data processing device for detecting the abnormal operation of a CPU is provided. The data processing device comprises a CPU, an interrupt counter, and a counter-abnormal-value detection circuit. The interrupt counter increments a count value based on an interrupt start signal which is outputted in response to an interrupt signal indicative of an interrupt request to the CPU and which indicates that the interrupt request has been accepted, and decrements the count value based on an end-of-interrupt signal which indicates that processing corresponding to the interrupt has completed. The counter-abnormal-value detection circuit detects abnormalities by comparing the count value with a predetermined value.

Abstract: A method includes detecting that a rate of temperature change in a server is above a threshold rate, changing the server to a lowest system performance state when the rate of the temperature change in the server is above the threshold rate, and reducing a fan speed to a minimum fan speed level when the rate of temperature change is above the threshold rate.

Abstract: An information processing device in which interrupts are generated when some events are occurred. The information processing device includes: an interrupt generating unit to generate an interrupt; an interrupt control unit to receive the generated interrupt, count an interrupt reception count per unit time, notify of the interrupt and delay, if the counted interrupt reception count per unit time exceeds a predetermined value, the interrupt notification; and an interrupt processing unit to process the notified interrupt.

Abstract: A cloud computer includes a base, a host, and a battery, in which the host includes a motherboard, a memory connected to the motherboard, and a base connector connected to the motherboard, and the base includes a host connector corresponding to the base connector of the host, and a plurality of input/output ports to connect to peripherals. The battery is mounted on the host and connects to the motherboard to provide electronic power to the motherboard, and the host is detachably connected with the base.

Abstract: Embodiments of systems, apparatuses, and methods for emulating an input/output Advanced Programmable Interrupt Controller are disclosed. In one embodiment, an apparatus includes a first interrupt controller having a first programming model, and emulation logic to emulate a second interrupt controller having a second programming model that is different from the first programming model. The emulation logic is also to mask one of a plurality of interrupt requests to the first interrupt controller for each of the plurality of interrupt requests handled by the emulation logic.

Abstract: Systems and methods of routing data units such as data packets or data frames that provide improved system performance and more efficient use of system resources. The disclosed systems and methods employ memory mapping approaches in conjunction with transaction ID tag fields from the respective data units to assign each tag value, or at least one range of tag values, to a specified address, or at least one range of specified addresses, for locations in internal memory that store corresponding transaction parameters. The disclosed systems and methods can also apply selected bits from the transaction ID tag fields to selector inputs of one or more multiplexor components for selecting corresponding transaction parameters at data inputs to the multiplexor components. The disclosed systems and methods may be employed in memory-read data transfer transactions to recover the transaction parameters necessary to determine destination addresses for memory locations where the memory-read data are to be transmitted.

Abstract: A method for managing the power consumed in a processor executing an application, the application including several processing phases, each of which is associated with a computational load. The method includes defining a first nominal mode of consumption, defining at least one second mode of low consumption, and formulating a decision function making it possible optionally to switch from the nominal mode of consumption to the mode of low consumption during the transition from one processing phase to another processing phase of the application.

Abstract: A storage system including: a storage apparatus including a plurality of storage devices on which a plurality of logical units is configured and a first controller that controls accesses to the plurality of logical units; and a file server coupled to said storage apparatus and including a second controller and a memory storing management information which indicates relationships between each of the plurality of logical units and each of a plurality of indicators; wherein the first controller, in response to a request to create a first folder with a first indicator, creates the folder on one or more first logical units included in the plurality of logical units, the one or more first logical units related to the first indicator.

Abstract: A data transmission system is provided. The data transmission system includes a serial peripheral interface (SPI) and a programmable controller. The SPI is coupled between a first device and at least one second device. The programmable controller controls the SPI to switch between a single port data transmission mode and a multi-port data transmission mode. When there are more than one second device coupled to the SPI, the SPI is switched to the multi-port data transmission mode so as to perform multi-port data transmission between the first device and the second devices. At this time, the first device concurrently transmits data to each of the second devices via a first transmission bus terminal, and concurrently receives data from each of the second devices via a second transmission bus terminal.

Abstract: One embodiment of the present invention sets forth a technique for metering a processing workload. A freeze time and run time are used to control whether or not pointers to command buffers are popped from a FIFO and the commands that generate a workload are read for processing. Smaller bursts of commands broken up by periods of idleness are coalesced by the workload metering to create larger bursts of commands during the run time and longer periods of idleness during the freeze time. Power saving features may be enabled during the periods of idleness to reduce the power consumption of the device performing the processing.

Abstract: An interface includes a port and a port control module. The port control module detects whether a remote device communicating with the port is one of a Universal Serial Bus (USB) device and a satellite digital transceiver (DT) device. The port control module selectively generates one of a USB configure signal and a satellite DT configure signal. A USB control module selectively configures the interface to communicate with the USB device when the USB configure signal is received. A satellite control module selectively configures the interface to communicate with the satellite DT device when the satellite DT configure signal is received.

Abstract: A method is provided in one example embodiment and includes communicating a query over a network to a plurality of entities that reside in a domain, the query including a request for data relating to energy use. The query can be generated by one or more computing devices belonging to the domain. A selected one of the computing devices can control power consumption for the entities in the domain. In other embodiments, a discovery protocol (DP) and a link layer discovery protocol (LLDP) is used for transporting events regarding the entities that connect or disconnect from the network. The entities send discovery events over a DP/LLDP protocol, identifying them as part of the domain. In yet other embodiments, the method includes querying a selected one of the entities to determine, if the selected entity moved to a certain energy level, an energy consumption value at the certain energy level.