Abstract: Systems and methods schedule periodic and non-periodic transactions in a multi-port bus environment. The method may comprise performing multiple search passes through a first array of endpoints to determine whether dispatch resources are available for active endpoints satisfying a set of sort criteria. When dispatch resources are not available for an endpoint, a sort level may be marked with a marker to indicate that an endpoint has not been serviced. After the active endpoints in the first array have been serviced by dispatching a periodic transaction to the endpoint or by marking a sort level corresponding to the endpoint, a non-periodic transaction may be dispatched to an active endpoint in a second array. In response to receiving an indication that the dispatch resources have become available, a subsequent search pass may be made through the first array, starting with a highest priority sort level that is marked with the marker.

Abstract: A serial communication method is applied in a computing device to communicate serially with any external serial device. The computing device includes a baseboard management controller (BMC) and an operating system (OS). The BMC includes at least one physical serial port. The method generates a virtual serial port for the OS by emulating serial port functionality of the physical serial port. When the BMC is initializing the physical serial port and a serial device is connected to the physical serial port, an interrupt handler is activated to handle an interrupt triggered to the BMC by the serial device. The interrupt handler is deactivated when the physical serial port has been initialized by the BMC.

Abstract: A system and method for efficient power transfer on a die. A semiconductor chip comprises on a die two or more computation units (CUs) utilizing at least two different voltage regulators and a power manager. The power manager reallocates power credits across the die when it detects an activity level of a given CU is below a given threshold. In response to receiving a corresponding number of donated power credits, each of the one or more selected CUs maintains a high activity level with a high performance P-state. When a corresponding workload increases, each CU maintains operation and an average power consumption corresponding to the high performance P-state by alternating between at least two different operational voltages. When the operational voltage drops during the alternation, the current drawn by the particular CU may exceed a given current limit. The power manager detects this current limit is exceeded and accordingly reallocates the power credits across the die.

Abstract: Suspendable interrupts are described that allow a processor to remain in an idle state for a longer period of time. Each suspendable interrupt defines a maximum delay value that specifies the maximum delay software associated with the interrupt can wait between a receipt of an interrupt signal associated with the suspendable interrupt and raising the interrupt for servicing by the software. The delay value allows suspendable interrupts to be masked when a processor is placed in the idle state if they can be dealt with at a next scheduled wake time of the processor, allowing the processor to potentially remain in the idle state for a longer period of time.

Abstract: A signal swing trimming apparatus calibrates a swing level of an output signal generated from a transmitting device to a receiving device including: a comparing device coupled to the output signal for comparing the swing level of the output signal with a target swing level and generating a comparison output signal, and an adjusting device coupled to the comparing device and the transmitting device for controlling the transmitting device to adjust the swing level of the output signal according to the comparison output signal, wherein the signal swing trimming apparatus is configured to calibrate the swing level of the output signal during a hand-shake process between the transmitting device and the receiving device.

Abstract: One embodiment of the present invention sets forth a technique for performing high-performance clock training. One clock training sweep operation is performed to determine phase relationships for two write clocks with respect to a command clock. The phase relationships are generated to satisfy timing requirements for two different client devices, such as GDDR5 DRAM components. A second clock training sweep operation is performed to better align local clocks operating on the client devices. A voting tally is maintained during the second clock training sweep to record phase agreement at each step in the clock training sweep. The voting tally then determines whether one of the local clocks should be inverted to better align the two local clocks.

Abstract: An information processing apparatus switches from a regular power mode to a power saving mode in the event that a first control unit does not process packets for a certain period of time. The information processing apparatus includes a packet table in which packets to be processed by the first control unit are registered, and a determining unit for determining whether the system of the information processing apparatus can switch to the power saving mode. In the event that the determining unit determines that the system can switch to the power saving mode, a network controller processes the packets based on the packet table.

Abstract: A control method for extender is proposed. A transmitting unit stops outputting image signal, voice signal or serial data to a receiving unit. A request signal is sent from the transmitting unit to the receiving unit by using the circuit through which the transmitting unit stops outputting image signal, voice signal or serial data to the receiving unit. Extended display identification data of a display device or peripheral data of a control device is sent from the receiving unit to the transmitting unit.

Abstract: In a computer system, a method of controlling coalescence of interrupts includes dynamically basing a current level of interrupt coalescing upon a determination of outstanding input/output (I/O) commands for which corresponding I/O completions have not been received. Deliveries of interrupts are executed on the basis of the current level and in an absence of enabling timing-triggered delivery of an interrupt.

Abstract: In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed.

Abstract: The present invention relates to power consumption, and specifically an apparatus, method, and computer readable medium to manage and control power consumption in computer systems. Specifically, the present invention manages power consumption by controlling the types of threads that are executed by the processor. The present invention monitors the resources of the system to determine the power consumption of the system. If the power consumption is too high, the present invention issues more low power threads to be executed by the processor.

Abstract: Various methods and structures related to clock distribution for flexible channel bonding are disclosed. One embodiment provides a clock network in physical media attachment (“PMA”) circuitry, a specific type or portion of system interconnect circuitry, arranged in pairs of channel groups. In one embodiment, clock generation circuitry blocks (“CGBs”) in each pair of channel groups receives outputs of multiple phased locked loop circuits (“PLLs”) which can be selectively utilized by the CGBs to generate PMA clock signals. In another embodiment, the CGBs can also select output of a clock data recovery (“CDR”)/transmit PLL circuitry block in one of the channels of a channel group of the pair of channel groups. In one embodiment, first groups of connection lines couple circuitry in a channel group pair such that a designated CGB in each channel group pair can provide clock signals to one or more of the channels in the channel group pair.

Abstract: The invention provides, in some aspects, a process, environmental, manufacturing, industrial or other such control system (hereinafter, “control system”) with enhanced, real-time change tracking. The system includes one or more configurable elements (e.g., field devices), a change tracking system that records of changes to those configurable elements (e.g., for compliance reporting, etc.) and a change detection system that responds to detected changes in configuration of those element(s) by inferring an identity of a person and/or device responsible for a change, the time of the change, and/or the reason for the change. This is unlike prior art systems, in which that such information must be specified, e.g., in a data entry form filled-in by the field engineer, operator or other who is making the change.

Abstract: An example of a method for facilitating split booting includes executing a base system image file of a system, initializing components of the first computing device, loading the extended system image file, and executing the extended system image file from the first computing device without booting the first computing device. The base system image file and an extended system image file of the system are built from a single executable system image file of the system. An example of a method for building system images includes building, as a single executable file, a system image file of a system and dividing the system image file into a base system image file and an extended system image file. An example of a machine-readable storage medium having code for carrying out the method, an apparatus having the machine-readable storage medium, and an apparatus having means for carrying out the method is disclosed.

Abstract: A serial port remote control circuit includes a first interface circuit, a control circuit, an output circuit, and a power circuit. The first interface circuit converts recommended standard 232 (RS232) level signals to transistor-transistor logic (TTL) level signals or vice versa. The control circuit is connected to the first interface circuit, to convert the TTL level signals to physical bus signal or vice versa. The output circuit is connected to the control circuit, to convert the received physical bus signals from the control circuit to network bus signals or vice versa. The power circuit outputs a first voltage and a second voltage converted from the first voltage to the control circuit, the first interface circuit, and the output circuit.

Abstract: Described are digital communication systems that transmit and receive parallel sets of data symbols. Differences between successive sets of symbols induce changes in the current used to express the symbol sets, and thus introduce supply ripple. A receiver adds compensation current to reduce supply ripple. The compensation current is calculated based upon prior data samples rather than the current symbols, and consequently increases the maximum instantaneous current fluctuations between adjacent symbol sets as compared with circuits that do not include the compensation. The frequency response of the power-distribution network filters out the increased data dependence of the local supply current, however, and consequently reduces the fluctuations of total supply current. Some embodiments provide compensation currents for both transmitted and received symbols.

Abstract: Described herein are techniques for dynamic memory frequency/voltage scaling to augment existing memory power management techniques and further improve memory power efficiency. Each operating point is defined as an operational state for the memory.

Abstract: A system and method for dynamic function based power control is disclosed. In one embodiment, a system includes a bridge unit having a memory controller and a communication hub coupled to the memory controller. The system further includes a power management unit, wherein the power management unit is configured to clock-gate the communication hub responsive to determining that each of a plurality of processor cores are in an idle state and that an I/O interface unit has been idle for an amount of time exceeding a first threshold. The power management unit is further configured to clock-gate the memory controller responsive to clock-gating the communication hub and determining that a memory coupled to the memory controller is in a first low power state. The power management unit may also perform power-gating of functional units subsequent to clock-gating the same.

Abstract: In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn via one or more physical units to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed.

Abstract: An invention is provided for transferring data between asynchronous clock domains. The asynchronous clock domains include a source clock domain operating with a source clock signal and a receiving clock domain operating with a receiving clock signal. The invention includes determining a phase shift relationship between the source clock signal and a signal. When the phase shift relationship is below a predetermined threshold the data is transferred between the source clock domain and the receiving clock domain using a first plurality of stage operations. When the phase shift relationship is above the predetermined threshold, the data is transferred between the source clock domain and the receiving clock domain using a second plurality of stage operations that delay data transfer an additional half period of the source clock signal.