Abstract: According to an aspect of the invention, an information processing apparatus includes a main board, an expanded CPU board connector, an external device connector, a detection unit. A first CPU is mounted on the main board. The expanded CPU board connector is disposed on the main board. An expanded CPU board is connectable to the expanded CPU board connector. A second CPU is mounted on the expanded CPU board. The external device connector is disposed on the main board. An external device is connected to the external device connector. The detection unit detects that the expanded CPU board is installed to the expanded CPU board connector. The first CPU controls the information processing apparatus to change a master of control of the information processing apparatus from the first CPU to the second CPU.

Abstract: In an embodiment, a command is received that requests movement of ownership of a target device from an origin compute element to a destination compute element. From the origin compute element, a translation of a virtual bridge identifier to a first secondary bus identifier, a first subordinate bus identifier, and a first MMIO bus address range is removed. To the destination compute element, a translation of the target virtual bridge identifier to a second secondary bus identifier, a second subordinate bus identifier, and a second MMIO bus address range is added. From a south chip that comprises the target virtual bridge, a translation of the target virtual bridge identifier to an identifier of the origin compute element is removed. To the south chip, a translation of the target virtual bridge identifier to an identifier of the destination compute element is added.

Abstract: To provide inter-LSI data synchronized transfer with a transfer throughput satisfying a required performance without causing an operation timing difference of the entire system even when a wiring delay between LSIs varies on an evaluation board and an actual device. A master (LSI1) outputs transfer data and a transfer synchronization clock signal to a slave (LSI2). For the edge of a clock signal used for data output at the master (LSI1), the slave (LSI2) latches input data by using a reverse edge. Moreover, upon data transfer from the slave (LSI2) to the master (LSI1), the master (LSI1) selects a latch timing of input data from a plurality of timings so that the transfer time to an internal circuit of the master (LSI1) side is identical regardless of which latch timing is selected.

Abstract: A system to synchronize processors includes one or more subsystems to receive an interrupt command, instruct a plurality of processors to enter an entry synchronization loop of an interrupt handler, determine by each of the plurality of processors whether all of the plurality of processors have entered their respective interrupt handler before exiting the entry synchronization loop, determine whether a timeout value has been reached, determine type of the interrupt command received and in response to the type of interrupt command received, determine whether to exit the entry synchronization loop after the timeout value has been reached.

Abstract: An apparatus includes a PHY assembly in electrical communication with a first interface assembly and with a second interface assembly, the PHY assembly configured to receive a power signal from a PSE, the PHY assembly having a first PHY and a second PHY. The first PHY is configured to receive a first data signal from the PSE through the first interface assembly via the frame-based computer networking connection and provide the first data signal to the second PHY for transmission to a network device through the second interface assembly via the frame-based computer networking connection. The second PHY is configured to receive a second data signal from the network device through the second interface assembly via the frame-based computer networking connection and provide the second data signal to the first PHY for transmission to the PSE through the first interface assembly via the frame-based computer networking connection.

Abstract: In general, the subject matter described in this specification can be embodied in methods, system and program products. A mobile computing device determines that the mobile computing device has physically paired with a docking system. Wireless communication between the mobile computing device and the docking system is automatically established in response to said determining that the mobile computing device has physically paired with the docking system. Data that encodes an audio signal is transmitted, by the mobile computing device and to the docking system as part of the wireless communication, so as to cause speakers of the docking system to audibly output the audio signal from the mobile computing device.

Abstract: In general, the subject matter described in this specification can be embodied in methods, system and program products. A mobile computing device determines that the mobile computing device has physically paired with a docking system. Wireless communication between the mobile computing device and the docking system is automatically established in response to said determining that the mobile computing device has physically paired with the docking system. Data that encodes an audio signal is transmitted, by the mobile computing device and to the docking system as part of the wireless communication, so as to cause speakers of the docking system to audibly output the audio signal from the mobile computing device.

Abstract: A method includes accepting for a first processor core of a plurality of processor cores in a multi-core system, a user-level interrupt indicated by a user-level interrupt message when an interrupt domain of an application thread executing on the first processor core and a recipient identifier of the application thread executing on the first processor core match corresponding fields in the user-level interrupt message.

Abstract: An apparatus for providing an interface for semiconductor processing equipment is disclosed. In some embodiments, an apparatus for providing an interface for semiconductor processing equipment having an interface card includes a display logic subsystem to provide an interface to one or more devices such as video and information displays, light pens, keyboards, computer mice, and warning light networks and alarms via a data and control bus; a bridge to provide access to the data and control bus; and a local computer subsystem coupled to the bridge and the display logic subsystem, wherein the local computer subsystem provides access to one or more remote devices.

Abstract: A method of improving memory power efficiency is disclosed. The method includes the following steps: a ground pin of a memory socket connecting to a power source, the ground pin is connected to a controller; the ground pin outputting a high level signal to the controller when the memory socket is without a memory component; and the controller sending an off-command to a regulator to cut off a supplying power to the memory socket after the controller receives the high level signal.

Abstract: In general, the subject matter described in this specification can be embodied in methods, systems, and program products. A mobile computing device is determined to have electrically coupled by physical contact with a docking system that is adapted to supply electrical power for charging the mobile computing device. The docking system is determined to be a first type of docking system from a plurality of types of docking systems. A first user interface profile that corresponds to the first type of docking system is selected from among a plurality of user interface profiles. Each of the plurality of user interface profiles corresponds to a respective type of docking system from the plurality of types of docking systems. The first user interface profile is presented by the mobile computing device in response to selection of the first user interface profile.

Abstract: In general, the subject matter described in this specification can be embodied in methods, systems, and program products. A mobile computing device is determined to have electrically coupled by physical contact with a docking system that is adapted to supply electrical power for charging the mobile computing device. The docking system is determined to be a first type of docking system from a plurality of types of docking systems. A first user interface profile that corresponds to the first type of docking system is selected from among a plurality of user interface profiles. Each of the plurality of user interface profiles corresponds to a respective type of docking system from the plurality of types of docking systems. The first user interface profile is presented by the mobile computing device in response to selection of the first user interface profile.

Abstract: System(s) and method(s) are provided for dynamically scaling switching frequencies and clock sources of switched mode power supplies (SMPSs) in a mobile station. Switching frequency is scaled to an optimal value in response to at least one of (i) a change in mode of operation for wireless communication employed by the mobile station, an additional mode of operation is triggered, (ii) a change in operation conditions of a set of loads associated with functionality of the mobile is determined, or (iii) an LO spur set-off by a SMPS in the presence of an interference signal with a frequency splitting from an operational band that matches the SMPS frequency or at least one of its harmonics. Switching frequencies can be selected from a lookup table, or through an analysis of switching frequencies available to the mobile and operational criteria. A set of clock sources can provide an ensemble of switching frequencies.

Abstract: In an embodiment, a system comprises a memory system configured to store a data structure. The data structure stores at least an interrupt request state for each destination in each of a plurality of guests executable on the system. The interrupt request state identifies which interrupts have been requested at the corresponding interrupt controller in the corresponding guest of the plurality of guests. A guest interrupt manager is coupled to receive an interrupt message targeted at a first destination in a first guest of the plurality of guests, and the guest interrupt manager is configured to update the interrupt request state in the data structure that corresponds to the first destination and the first guest.

Abstract: The present invention discloses a switching interface method for multi-interface storage device having a transmission interfaces and a predetermining list that stores different priority weights for the transmission interfaces. When the storage device connects to a computer, the switching interface method is executed and one of the transmission interfaces is selected to communicate with the computer according to the priority weight in sequence. In addition, a user's interface is also provided for the user, and the user can switch other transmission interface of the multi-interface storage device to link to the computer. Therefore, the multi-interface storage device may link to most of the computers and successfully communicate with the computer.

Abstract: A communication method and a master-slave system, for a field bus configures according to the AS-interface standard, are disclosed. Such a master-slave system for a field bus configured according to the AS-interface standard connects a master to a number of slaves. This field bus forms a first communication channel for the master and the slaves. In at least one embodiment, the master communicates with the slaves in sequence via telegrams, which are each uniquely associated with one of the slaves. Between the master and slaves a second communication channel is provided in at least one embodiment, via which one of the telegrams may be repeated, in addition to the first communication channel, if the communication of said telegram via the first communication channel has failed.

Abstract: An electronic timer system includes a counter-based time generator (10) for continuously generating raw base time, and a translator (20) for translating between raw base time and local precise time using configurable parameter values. The timer system can be used for generating local precise time by capturing a raw base time value from the counter-based time generator (10) in response to an external event such as a trigger pulse, and using the translator (20) to calculate local precise time from the raw base time value and the parameter values. The timer system can also be used for generating a precisely timed output signal using the translator (20) for translation from precise time of a desired timing event to raw base time. This novel design enables simple and cost-effective practical implementations, and may also support power effective operation of the timer system.

Abstract: The described implementations relate to energy-aware server management. One implementation involves an adaptive control unit configured to manage energy usage in a server farm by transitioning individual servers between active and inactive states while maintaining response times for the server farm at a predefined level.

Abstract: A computer system has at least one supply device, at least one system component with a data-processing device and at least one communications device. The supply device has at least one programmable control module that is supplied with an operating energy by a voltage source coupled to the at least one supply device and operated independently thereof.

Abstract: A computer system may include a connecting hub having a plurality of docking regions and be configured to provide to each docking region electrical power, a data network interface, a cooling fluid supply and a cooling fluid return; and a plurality of shipping containers that each enclose a modular computing environment that incrementally adds computing power to the system. Each shipping container may include a) a plurality of processing units coupled to the data network interface, each of which include a microprocessor; b) a heat exchanger configured to remove heat generated by the plurality of processing units by circulating cooling fluid from the supply through the heat exchanger and discharging it into the return; and c) docking members configured to releaseably couple to the connecting hub at one of the docking regions to receive electrical power, connect to the data network interface, and receive and discharge cooling fluid.