Abstract: A solution for setup and optimization of a data transfer path in extended computer systems, where the I/O system is virtualized. The solution achieves advantageous results via a mechanism that automates the configuration of multiple data path components. The solution achieves initial optimization and then automates continual optimization of the data path through monitoring of changes and through dynamic adjustment of system resources and data transfer characteristics.

Abstract: An interrupt reducing device driver module reduces the rate at which interrupts from a peripheral burden a processor. The interrupt reducing device driver determines when data is associated with the interrupt. When data is present, such as when indicated by an interrupt status register, further interrupts are masked and a buffer associated with the peripheral is read-out. This read-out continues while data is present in the buffer. Once no further data is present, the data interrupts are unmasked. Reduction in the rate of interrupts prevents resource starvation and improves overall system response. Additionally, the processor and associated components are able to enter and remain in low power modes, improving battery life.

Abstract: Disclosed herein is a deadlock avoidance circuit including: a previous-transaction-information management section; a transaction-issuance-termination determination section; and a response-outputting control section.

Abstract: Various embodiments of methods and systems for controlling and/or managing thermal energy generation on a portable computing device are disclosed. Data discarded from one or more processing core registers may be monitored and analyzed to deduce individual workloads that have been processed by each of the cores over a unit of time. From the deduced workloads, the power consumed by each of the cores over the unit of time in order to process the workload can be calculated. Subsequently, a time dependent power density map can be created which reflects a historical and near real time power consumption for each core. Advantageously, because power consumption can be correlated to thermal energy generation, the TDPD map can be leveraged to identify thermal aggressors for targeted, fine grained application of thermal mitigation techniques. In some embodiments, workloads may be reallocated from the identified thermal aggressors to the identified underutilized processing components.

Abstract: A computer system which shortens standby time of CPUs and improves CPU processing efficiency of a performance mode upon switching from the performance mode (parallel operation) to a safety mode (master/checker operation) is provided. In a computer system including: at least two CPUs; a programmable interrupt controller for interrupting the CPUs; and a comparator for mutually comparing outputs of the CPUs, switching between the performance mode of executing mutually different processes by the CPUs, respectively, to improve performance and the safety mode of executing mutually the same processes by the CPUs and collating results by the comparator to detect failure can be carried out; CPUs to be interrupted can be set for each interrupt factor; and whether the performance mode is to be executed or the safety mode is to be executed can be set for each interrupt factor.

Abstract: A processor integrated circuit has one or more processor cores and a power management controller in a North-Bridge that generates a first power state recommendation for the one or more processor cores. The North-Bridge also receives a second power state recommendation from a South-Bridge integrated circuit. The North-Bridge determines a final power state for the one or more processor cores based on the first and second power state recommendations.

Abstract: Methods of operation and interrupt controllers for generating interrupt signals to a unit, which could enter an active mode and a non-active mode, are disclosed. The interrupt controllers have interrupt logic (204) adapted for receiving requests for interrupt, activity mode logic (202) adapted for receiving information whether the unit is in non-active mode, and delay control logic (203) adapted for delaying the interrupt to the unit when the received information indicates that the unit is in non-active mode.

Abstract: System and method for facilitating data transfer between logic systems and a memory according to various conditions. Embodiments include systems and methods for facilitating and improving throughput of data transfers using a shared non-deterministic bus, a system and method for managing a memory as a circular buffer, and a system and method for facilitating data transfer between a first clock domain and a second clock domain. Embodiments may be implemented individually or in combination.

Abstract: Methods and systems for advanced interrupt processing and scheduling are provided. The system comprises a memory operable to store interrupt priorities, an interface, and a processor operable to acquire incoming interrupts and to handle the incoming interrupts according to the interrupt priorities. The processor is also operable to receive interrupt processing criteria from the interface (sent, for example, from a device not directly coupled with the system), and to modify the interrupt priorities of the memory based upon the interrupt processing criteria without losing incoming processing requests for the system. Additionally, the processor is operable to process the incoming interrupts according to the modified interrupt priorities responsive to modifying the interrupt priorities.

Abstract: The present invention discloses a method and a system for power saving management. The method includes: a new power consuming state attribute added for existing device object of the communication network management system is configured, wherein the power consuming state attribute is used for indicating the power consuming state of the electrical energy; performing the power saving management on the device by setting the power consuming state of the object corresponding to the device. With the above technical solution, the division of the state information could be clearer and more efficient, meanwhile, the redundancy can be eliminated, in addition, has the feather of wide adaptability.

Abstract: An automation appliance (6) having at least one field bus interface (12) for connection to a field bus (2) and transmission of data packets (DP) with process data (PD) via the field bus (2) and having at least one local bus interface (21) for connection to a local bus (7) and transmission of process data (PD) between field devices (9a, 9b, 9c) connected to the local bus (7) and the automation appliance (6), and having means for converting the data packets (DP) coming from the field bus (2) into a data stream (DS) for the local bus (7) and for converting the data stream (DS) sent from the local bus (7) to the automation appliance (6) into data packets (DP) for the field bus (2) is described.

Abstract: A method for data exchange via a bus system, wherein an amount of data determined for data exchange is composed of a plurality of data packets, which data packets are to be transmitted in a predetermined sequence from a second participant of the bus system to a first participant of the bus system, wherein, for data exchange, a first data query is sent from the first participant to the second participant, and wherein, as a reply to the first data query, a first data packet is sent from the second participant to the first participant. Especially after the first participant has received the first data packet, a second data query is sent from the first participant to the second participant via the bus system, and as a reply to the second data query, a second data packet is sent from the second participant to the first participant. The second data packet is either the first data packet or a data packet following the first data packet in the predetermined sequence.

Abstract: Systems and methods schedule periodic and non-periodic transactions in a multi-speed bus environment that includes in a downstream hub a data forwarding component, such as a USB transaction translator, which accommodates communication speed shifts at the hub. The method may comprise receiving a split packet request defining a transaction with a device, tagging the request with an identifier allocated to the data forwarding component, storing the request in a transaction list associated with the identifier, initiating transfer of payload data, and updating a counter associated with the identifier to reflect an amount of payload data for which transfer was initiated. The identifier may have associated therewith a counter for tracking a number of bytes-in-progress to the data forwarding component and one or more transaction lists configured to store a plurality of split packet requests awaiting execution and state information regarding an execution status of the requests.

Abstract: An apparatus and method of low latency precedence ordering check in a PCI Express (PCIe) multiple root I/O virtualization (MR-IOV) environment. The precedence ordering check mechanism aids in enabling a port to comply with PCIe MR-IOV ordering rules. A posted information array mirrors a posted transaction queue, storing precedence order indicator and Virtual Hierarchy (VH) tag information for corresponding posted transaction entries stored in the posted transaction queue. The selector queries the posted information array periodically, such as each cycle, to determine whether the non-posted/completion transaction at the output of their respective queues have any preceding posted transactions of the same VH somewhere in the posted queue.

Abstract: A multi-use physical (PHY) architecture that includes a PHY connection that includes one or more bit lines and that is communicatively coupled to a first processor. The PHY connection is configurable to carry signals between the first processor and a second processor, or between the first processor and a memory. The one or more bit lines are configured to carry signals bi-directionally at a first voltage when the PHY connection is configured to carry signals between the first processor and the memory. The one or more bit lines are configured to carry signals uni-directionally at a second voltage when the PHY connection is configured to carry signals between the first processor and the second processor. The second voltage is different than the first voltage.

Abstract: A method and system for dynamically managing a bus within a portable computing device (“PCD”) are described. The method and system include monitoring software requests with a bus manager. The bus manager determines if a software request needs to be converted into at least one of an instantaneous bandwidth value and an average bandwidth value. The bus manager then converts the software requests into these two types of values as needed. The bus manager calculates a sum of average bandwidth values across all software requests in the PCD. With these values, the bus manager may dynamically adjust settings of the bus based on instantaneous or near instantaneous demands from the master devices. This dynamic adjustment of the bus settings may afford more power savings for the PCD during low loads or during sleep states.

Abstract: A linkup state generating method for generating a state in which linkup is completed in first and second information processing apparatuses, the first and second information processing apparatuses each including a linkup function of, with parameter exchange, comparing parameters included in the first and second information processing apparatuses and adjusting specifications of the parameters so that the specifications of the parameters match each other, the linkup state generating method including setting, from the outside, a parameter in the first information processing apparatus so that a specification of the parameter included in the first information processing apparatus matches a specification of a parameter included in the second information processing apparatus, and sending, from the first information processing apparatus, a signal received from the second information processing apparatus to the second information processing apparatus in a manner that the second information processing apparatus recogni

Abstract: An embedded system includes an ARM processor and a number of b-bit peripheral processors connected to the ARM processor through a converting chip. The ARM processor includes pins P0˜Pa-1 divided into teams T1˜TN, each of which includes b pins, a and b are integral multiple of 8, wherein a=N×b. The number of the peripheral processors is N and each team corresponds to one peripheral processor. The converting chip reads an a-bit data from the ARM processor, converts the data into a plurality of b-bit data, and transfers each b-bit data to a peripheral processor, where the number of the b-bit data is N. The converting chip further reads one b-bit data from each peripheral processor in sequence, converts the read plurality of b-bit data into an a-bit data, and transfers the a-bit data to the ARM processor.

Abstract: A system and method for reducing overall connection latencies in a SAS expander is disclosed. The SAS expander includes a plurality of ports and a route lookup table configured for providing a central resource for routing information for the ports. The SAS expander also includes a plurality of connection history caches (CHCs) associated with the ports, each CHC is configured for storing at least one successfully established connection record. Upon receiving a connection request at a particular port, that particular port may determine whether a matching connection record for the connection request is stored in its corresponding CHC. If the matching connection record is stored in its corresponding CHC, a connection may be established in response to the connection request based on the matching connection record. However, if no matching connection record is found in its corresponding CHC, the connection may be established utilizing the route lookup table.

Abstract: A power management method of an image forming apparatus which communicates with at least one terminal device supporting a universal plug and play (UPnP) protocol, including: setting power save mode information which includes a plurality of levels corresponding to the UPnP protocol to the image forming apparatus; storing the set power save mode information; receiving a command to enter a first power save mode among the plurality of levels from the terminal device; comparing the received command to enter the first power save mode with the stored power save mode information; and entering a power save mode by the image forming apparatus corresponding to the received command to enter the first power save mode. With this configuration, the image forming apparatus supporting a UPnP protocol categorizes power save modes by using a low power protocol of the UPnP protocol, and can reduce unnecessary power consumption and improves usability.