Abstract: Generally discussed herein are Low Density Parity Check (LDPC) circuit layouts. An example LDPC circuit can include combinational logic and a plurality of memory units. Each of the plurality of memory units can be electrically coupled to each other and the combinational logic, and the plurality of memory units can be situated in a ring-like configuration.

Abstract: Disclosed is a method for data transmission, comprising: generating the parity check matrix on the basis of the generating sequence corresponded to the preserved row generator; encoding the input data by the generated matrix obtained by said parity check matrix, and obtaining the output data comprising the parity check information. Also provided in the present invention is an apparatus for data transmission. The method and apparatus of the present invention could make the parity check matrix take the minimum storage space.

Abstract: A method for detecting errors in a transfer of data from a transmitter to at least one receiver includes coding the data together with address information identifying the receiver in a series of data packets and transferring the data and the address information using the data packets. The method also includes generating, at the transmitter, a check value for each data packet and transferring the check value with/in the data packet to the receiver. The method further includes comparing, at the receiver, the check value with an expectation value, wherein an error is detected in the event of a deviation. For each data packet to be transmitted, the method includes calculating a number sequence value from the address information using a first calculation rule, generating the check value from the sequence value using a second calculation rule and transmitting the data packet with the check value to the receiver.

Abstract: A method for reordering a test pattern set for testing an integrated circuit is disclosed. A productivity index is computed for each test pattern in a test pattern set. The productivity index of a first test pattern and the productivity index of a second test pattern are compared. If the productivity index of the second test pattern is larger than the productivity index of the first test pattern, the location of the first test pattern and the second test pattern are swapped.

Abstract: Apparatuses and methods associated with shaping codes for memory are provided. One example apparatus comprises an array of memory cells and a shaping component coupled to the array and configured to encode each of a number of received digit patterns according to a mapping of received digit patterns to shaping digit patterns. The mapping of received digit patterns to shaping digit patterns obeys a shaping constraint that limits, to an uppermost amount, an amount of consecutive digits of the shaping digit patterns allowed to have a particular digit value.

Abstract: A method and an apparatus for transmitting and receiving a packet in a broadcasting and communication system are provided. The method includes splitting a source packet block including source packets into a plurality of source packet subblocks, converting the source packet subblocks to source symbol subblocks, respectively, generating a plurality of first repair symbol blocks by encoding the source packet subblocks using a first error correction code, configuring an error correction source packet by adding a source error correction payload IDentifier (ID) to source symbols included in the source symbol subblocks and configuring an error correction repair packet by adding a repair error correction payload ID to repair symbols included in the first repair symbol subblocks, and transmitting the error correction source packet and the error correction repair packet.

Abstract: The present invention develops a wireless communication transmitting scheme which allows a desired receiver to stably receive data so that data are not tapped by a third party when a transmitter transmits data to the receiver in a wireless scheme. In particular, the third party not a desired receiver taps, a bit error probability of received data is maintained to have about 50%, so that the third party cannot substantially obtain valid data. A suggested scheme of the present invention may transmit security data in a state that a transmitter and a receiver do not have a secret key unlike an existing cryptography.

Abstract: A semiconductor memory device includes a memory cell array including a normal region for storing a plurality of data, an error information region for storing a plurality of error information data corresponding to the plurality of normal data, respectively, and a redundancy region for replacing the normal region, an error detection unit suitable for detecting an error on the plurality of data in response to the plurality of error information data, and storing an error location information, which indicates a storage region of a data having an error in the normal and redundancy regions, based on an error detection result, and a repair operation unit suitable for replacing the storage region, which is indicated by the error location information, by the redundancy region during a repair operation period.

Abstract: Systems, methods, and other embodiments associated with LDPC decoder architectures are described. According to one embodiment, a method includes decoding codeword bits with a high throughput LDPC decoder and when the decoding of the codeword bits with the high throughput LDPC decoder is unsuccessful, decoding the codeword bits with a low throughput LDPC decoder.

Abstract: An encoding method generates an encoded sequence by performing encoding of a given coding rate according to a predetermined parity check matrix. The predetermined parity check matrix is a first parity check matrix or a second parity check matrix. The first parity check matrix corresponds to a low-density parity check (LDPC) convolutional code using a plurality of parity check polynomials. The second parity check matrix is generated by performing at least one of row permutation and column permutation with respect to the first parity check matrix. An eth parity check polynomial that satisfies zero, of the LDPC convolutional code, is expressible by using a predetermined mathematical formula.

Abstract: A system, method, and tangible computer readable medium for chip debug is disclosed. For example, the system can include a plurality of functional blocks, a debug path, and a debug bus steering module. The debug path couples the plurality of functional blocks in a daisy chain configuration, where an end functional block from the plurality of functional blocks is at an end of the daisy chain configuration. The debug bus steering module is configured to pass one or more debug signals associated with a first functional block from the plurality of functional blocks along the debug path to the end functional block while a second functional block from the plurality of functional blocks performs one or more power gating cycles.

Abstract: Methods and systems for communicating in a wireless network may distinguish different types of packet structures by modifying the phase of a modulation constellation, such as a binary phase shift keying (BPSK) constellation, in a signal field. Receiving devices may identify the type of packet structure associated with a transmission or whether the signal field is present by the phase of the modulation constellation used for mapping for the signal field. In one embodiment, the phase of the modulation constellation may be determined by examining the energy of the I and Q components after Fast Fourier Transform. Various specific embodiments and variations are also disclosed.

Abstract: A method for estimating a block error rate and a communication device are applied to the field of communications technologies. The method for estimating a block error rate includes: decoding N received coded code blocks to obtain multiple posterior probabilities APPs, where N is a natural number greater than 1; obtaining, according to the multiple posterior probabilities APPs and a preset policy, a result indicating that the decoding of each coded code block is correct or incorrect, where the preset policy includes: when a sum of absolute values of the multiple APPs is greater than or equal to a preset threshold, the decoding is correct; and obtaining a decoding block error rate according to a result indicating whether the decoding of the N coded code blocks is correct. In this way, the estimation of a decoding block error rate is implemented.

Abstract: In one form a method of encoding a data word for serial transmission is provided, where a data word comprising a plurality of data bits is received, an invert bit having a bit value is appended to the data word, the data bits and invert bit are scrambled, ECC check bits are generated, and the data bits, invert bit, and ECC check bits are shuffled together to form an encoded word to be transmitted from a transmitter. A receiver may decode by implementing a decode process with error correction. The encoded word may also be DC balanced by checking the disparity of the bits to be encoded against a running disparity to invert or not the bits. An integrated circuit serializer/deserializer comprises hardware to perform encoding and/or decoding. A hardware functional verification system may implement the disclosed encoding/decoding for interconnections between emulation chips.

Abstract: In one embodiment, the data storage apparatus includes a control unit configured to decode at least one input command and configured to generate at least one of a read signal and a start signal in response to the input command. The start signal indicates to start an internal mode determination process. The data storage apparatus also includes a memory unit configured to output data in response to the read signal, and a coding unit configured to start and perform the internal mode determination process in response to the start signal. The internal mode determination process includes autonomously determining a coding mode, and the coding unit is configured to code the output data based on the determined coding mode to produce coded data.

Abstract: A scan flip flop includes a partial multiplexer coupled to a master latch. The partial multiplexer is configured to receive a scan enable (SCAN) where the partial multiplexer includes an OR gate coupled to a tri-stated AND gate. A tri-state inverter is coupled to an output of the master latch and a slave latch is configured to receive an output of the tri-state inverter. A delay element is coupled to the slave latch, where the delay element is configured to delay a first output of the slave latch in response to the scan enable to generate a dedicated scan output.

Abstract: An encoding method generates an encoded sequence by performing encoding of a given coding rate according to a predetermined parity check matrix. The predetermined parity check matrix is a first parity check matrix or a second parity check matrix. The first parity check matrix corresponds to a low-density parity check (LDPC) convolutional code using a plurality of parity check polynomials. The second parity check matrix is generated by performing at least one of row permutation and column permutation with respect to the first parity check matrix. An eth parity check polynomial that satisfies zero, of the LDPC convolutional code, is expressible by using a predetermined mathematical formula.

Abstract: Data objects are delivered over a packet-switched network and receivers receive encoded symbols, such as repair symbols, broadcast or multicast, with sufficient information to form requests for additional symbols as needed based on what source symbols or sub-symbols are needed or missing. The requests can be made in a unicast or request fashion. Requesting and broadcasting might be done by different entities. A broadcast server can generate and store repair symbols while a source server can store content in source form. A request can be a unicast HTTP byte-range request, such as a URL, starting position and length. Requests might be aligned with starting positions of files. A receiver can calculate starting and ending byte positions of symbols or sub-symbols in a file and get indications that conventional HTTP servers are usable for file repair. Repair servers can request broadcast of repair data when byte-range requests from multiple receivers overlap.

Abstract: A differential memory device includes of memory locations having a direct memory cell and a complementary memory cell. A corresponding method includes receiving a request of reading a selected data word associated with a selected code word, reading a differential code word representing a differential version of the selected code word, verifying the differential code word according to an error correction code, setting the selected data word according to the differential code word in response to a positive verification. The method further includes reading at least one single-ended code word representing a single-ended version of the selected code word, verifying the single-ended code word according to the error correction code, and setting the selected data word according to the single-ended code word in response to a negative verification of the differential code word and to a positive verification of the single-ended code word.

Abstract: A semiconductor device may include a first encoding unit configured to encode first data into an anti-drift code, and a second encoding unit configured to add parity information to the anti-drift code.