Abstract: A testing apparatus includes a scenario processing unit that executes a test scenario for operating the testing apparatus to imitate the operation of a base station, a communication unit capable of transmitting and receiving a message to and from a mobile communication terminal, a layer processing unit for processing a message for each layer, a log data storing unit for storing log data indicating transmission of messages between the layers, and a display controller for creating a transmission schedule based on the extracted data associated with system information and causing a display unit to display the transmission schedule. The transmission schedule is written in a tabular form in which a block type of the system information is displayed at a position to which a frame for transmitting the system information is allocated.

Abstract: Forward Error Correction (FEC) techniques that generate independently decodable resource blocks are beneficial for Successive Interference Cancellation (SIC) demodulation. One FEC technique for generating independently decodable resource blocks includes mapping locally decodable FEC codeblocks into unique resource blocks such that substantially all of the bits of the FEC codeblock are carried within a single resource block. The locally decodable FEC codeblocks can be generated from different FEC encoding modules or from a common FEC encoding module. Another technique for generating independently decodable resource blocks includes encoding a stream of information bits into low-density parity-check (LDPC) codeblocks having high ratios of inward peering parity bits. These high ratios of inward peering parity bits allow substantial portions of each LDPC codeblock to be decoded independently from information carried by other LDPC codeblocks.

Abstract: An example of the invention includes a process and apparatus combining test modalities that collates data, processes it into a standard format, evaluates trends and interrogates via an expert system can increase efficiency and yield greater confidence in testing of parts in a variety of supply chain segments. An exemplary process and test system can collect a variety of test data as pre-processed raw data from a plurality of modalities as an evaluation database. The evaluation database post-processes said raw data via data analysis output to an expert system and decision engine as exemplary rule sets. The decision engine generating a probability that a microelectronic device is unauthorized, does not meet specification(s), is defective or counterfeit.

Abstract: An error correction code block including dual-syndrome generators, which may process a plurality of successive code word without latency, is configured to calculate syndrome values of a corresponding even numbered codeword among the plurality of code words by using one of the dual-syndrome generators, and is configured to calculate syndrome values of a corresponding odd numbered codeword among the plurality of code words by using the other of the dual-syndrome generators.

Abstract: A semiconductor device includes a scan chain that scans out latch signals of a plurality of latches; a first switch that selects any one of an output signal of a combinational circuit and a signal of the scan chain; a first latch that is inserted into the scan chain and receives an output signal of the first switch; a second latch that receives an output signal of the combinational circuit; and a second switch that selects any one of a latch signal of the first latch and a latch signal of the second latch and supplies the selected one to a combinational circuit in a following stage.

Abstract: A bypass mechanism allows a memory controller to transmit requested data to an interconnect before the data's error code has been decoded, e.g., a cyclical redundancy check (CRC). The tag, tag CRC, data, and data CRC are pipelined from DRAM in four frames, each having multiple clock cycles. The tag includes a bypass bit indicating whether data transmission to the interconnect should begin before CRC decoding. After receiving the tag CRC, the controller decodes it and reserves a request machine which sends a transmit request signal to inform the interconnect that data is available. Once the transmit request is granted by the interconnect, the controller can immediately start sending the data, before decoding the data CRC. So long as no error is found, the controller completes transmission of the data to the interconnect, including providing an indication that the data as transmitted is error-free.

Abstract: A data encoding circuit and a corresponding method is provided. The data encoding circuit includes a first data formatter in communication with an encoder section. The first data formatter is configured to receive blocks of source data in serial and output parallel two dimensional source data. The encoder receives the parallel two dimensional source data and that computes a plurality of serial row parity bits and a plurality of parallel column parity bits of an error correcting code from the parallel two dimensional source data. A second data formatter communicates with the encoder section and receives the parallel column parity bits and outputs serial column parity bits.

Abstract: A mechanism is described for achieving high memory reliability, availability, and serviceability (RAS) according to one embodiment of the invention. A method of embodiments of the invention includes detecting a permanent failure of a first memory device of a plurality of memory devices of a first channel of a memory system at a computing system, and eliminating the first failure by merging a first error-correction code (ECC) locator device of the first channel with a second ECC locator device of a second channel, wherein merging is performed at the second channel.

Abstract: A test apparatus includes a test apparatus may include a core suitable for accommodating a semiconductor device to be tested, a wrapper data register suitable for storing data used for testing the semiconductor device, and a bandwidth controller suitable for adaptively controlling a data bandwidth between the core and the wrapper data register according to the semiconductor device to be tested.

Abstract: An on-chip clock controller includes a clock-control chain configured to shift first clock-control bits in serial and output the first clock-control bits to a first clock domain in parallel in response to a clock-control scan clock provided from outside of a chip, and a first domain clock generator, the first domain clock generator configured, during a test mode, to generate a first internal clock by selectively outputting a first data scan clock provided from outside of the chip or a first functional clock generated from inside of the chip.

Abstract: Semiconductor memory device and method of operating same includes reading data stored in memory cells of a page; performing an error correction loop (ECC loop) including performing an error checking and correcting operation (ECC) on the read data; determining a number of bit errors in the read data; and when the number of bit errors is greater than a maximum number of correctable bits, incrementing the number of ECC iterations (ECC count) and increasing the maximum number of correctable bits; storing the ECC count until the number of bit errors is less than the maximum number of correctable bits; and programming corrected data to the memory cells when the stored ECC count is more than preset number.

Abstract: An encoding method generates an encoded sequence by performing encoding of a given coding rate according to a predetermined parity check matrix. The predetermined parity check matrix is a first parity check matrix or a second parity check matrix. The first parity check matrix corresponds to a low-density parity check (LDPC) convolutional code using a plurality of parity check polynomials. The second parity check matrix is generated by performing at least one of row permutation and column permutation with respect to the first parity check matrix. An eth parity check polynomial that satisfies zero, of the LDPC convolutional code, is expressible by using a predetermined mathematical formula.

Abstract: Apparatus and methods provide relatively low uncorrectable bit error rates, low write amplification, long life, fast and efficient retrieval, and efficient storage density such that a solid-state drive (SSD) can be reliably implemented using various types of memory cells, including relatively inexpensive multi-level cell flash. One embodiment intelligently coordinates remapping of bad blocks with error correction code control, which eliminates the tables used to avoid bad blocks.

Abstract: Address error detection including a method that receives a read address corresponding to a read location in a memory. Data is read from the read location in the memory. The data is transformed at a computer based on the data and the read address to produce read data. Error correction codes (ECC) bits associated the read data are read from the read location in the memory. The ECC bits were generated based on the write data. It is determined whether the read data has an address error responsive to the read data and the ECC bits associated with the write data. An error is generated in response to determining that the read address has an address error.

Abstract: TTI bundling is included for Msg3 transmissions in LTE communications. A reserved group of preambles or reserved set of random access preamble transmission opportunities are used to indicate user equipment (UE) need of uplink (UL) transmission of a TTI-bundled Msg3. The UE transmits the same redundancy version for transmissions within a TTI bundle as the eNB expects even if any of the transmissions are dropped due to collisions with an Msg3 transmission. In addition, co-existence of TTI bundling and UL semi-persistent scheduling (SPS) for TDD DL/UL configurations is provided using SPS intervals which are multiples of various fixed time periods.

Abstract: A method of storing a set of metadata bits associated with each of multiple data words includes combining the set of metadata bits with each of the multiple data words to generate multiple extended data words. The method includes encoding each of the multiple extended data words to generate multiple codewords and puncturing each of the multiple codewords to generate multiple punctured codewords, where in each of the punctured codewords the set of metadata bits is removed. The method includes storing the multiple punctured codewords, transforming the set of metadata bits to generate a set of transformed metadata bits, and storing the set of transformed metadata bits.

Abstract: An encoder provides (2t?1) redundant symbols in a sequence of n coded symbols, and a decoder corrects up to t erroneous symbols in the sequence of n coded symbols corrupted by a plurality of symbol errors. The decoder uses an improved decoding method, the method solving a plurality of matrix equations, each matrix equation associated with a hypothetical location of error. By monitoring a plurality of solutions associated with hypothetical locations of error, a processor determines the actual number of errors, the locations of the erroneous symbols in the sequence of n symbols, and the erroneous symbol value at each error location. The improved decoder includes erasure processing and a correct symbol determination method similar to erasure processing.

Abstract: Systems and methods are provided for encoding and transmitting codewords. A message is encoded in two encoders. For at least one of the two encoders, the message is algebraically modified prior to being encoded. In a specific example, the message is algebraically modified prior to being encoded in each of two traditionally non-systematic encoders, with the result that the output is equivalent to that of a turbo encoder.

Abstract: The method according to the invention relates to the decoding of a sequence of symbols, the sequence of symbols having been generated by: calculating a CRC value for an initial message; combining the initial message and the CRC value so as to produce a transformed message; and, encoding the transformed message. The decoding comprises: generating a number of path hypotheses via a trellis diagram corresponding to the trellis diagram of a finite-state machine comprising the encoder and the CRC generator, in which the encoder and the CRC generator are supplied with the same input. According to a preferred embodiment of the method, the trellis diagram is adapted to take into account bit stuffing possibly inserted in the transformed message before encoding.

Abstract: A transmission apparatus includes an encoder that codes a data sequence with a parity check matrix, wherein the data sequence includes a final information bit sequence and virtual information bits, and outputs the final information bit sequence and a parity sequence, as LDPC codes, and a transmitter that transmits the LDPC codes as a transmission data. A column length of the parity check matrix is longer than a total length of the final information bit sequence and the parity sequence, by a length of the virtual information bits that are set to “0” and are not transmitted. The total length of the final information bit sequence and the parity sequence has a sequence length corresponding to a length from a first column to a predetermined column of the parity check matrix. The encoder generates the LDPC codes by using the first column to the predetermined column among one or more column(s) of the parity check matrix.