Patents Examined by Sam Rizk
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Patent number: 9344226Abstract: This transmission comprising a first transmission of a packet (52), comprising the steps consisting in: a first processing (54) of said packet (52) to obtain a first packet (56); and a coding (57, 59) of the first packet (56); wherein, when the first coded packet is received erroneous, the method comprises a second transmission of said packet, comprising: the steps implemented in the transmitter, consisting in: a second processing (84) of said packet (52) to obtain a second packet (86); and a coding (87, 89) of the second packet (86); and the steps implemented in the receiver, consisting in: a modification of the first and/or the second coded packets to obtain two packets in which the difference due to the first and second processings is compensated for: a combination (110) of both packets according to a HARQ procedure; and a decoding (112) of the combined packet.Type: GrantFiled: October 5, 2012Date of Patent: May 17, 2016Assignees: CASSIDIAN SAS, CASSIDIAN FINLAND OYInventors: Philippe Mege, Christophe Molko, Marc Mouffron, Christophe Brutel
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Patent number: 9343179Abstract: A system and method for performing three scans for testing an address decoder and word line drive circuits is disclosed. The first scan determines whether only one word line is selected. The second scan determines whether the word line rise time to a target voltage level is within a specified time. Finally, the third scan determines whether the correct word line was selected.Type: GrantFiled: December 18, 2013Date of Patent: May 17, 2016Assignee: Infineon Technologies AGInventors: Thomas Nirschl, Jens Rosenbusch, Ulrich Backhausen, Thomas Kern, Thomas Liebermann
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Patent number: 9336079Abstract: A system and method including a parity bit encoder for encoding bits of data to be transmitted with first and second parity check bits to produce successive block of bits. Each of the blocks of bits are Gray mapped to a plurality of associated QAM symbols that are modulated onto an optical wavelength and transmitted to a receiver. A de-mapper corrects for 90 degree and 180 degree cycle slip using parity indicated by the first and second parity bits.Type: GrantFiled: December 11, 2013Date of Patent: May 10, 2016Assignee: TYCO ELECTRONICS SUBSEA COMMUNICATIONS LLCInventors: Hongbin Zhang, Hussam G. Batshon
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Patent number: 9336100Abstract: Debugging techniques performed post-silicon, but with reference to pre-silicon phase data and/or reference model data. For example, one debugging technique is as follows: (i) receiving a first memory location that is subject to a miscompare between an associated simulation value for the first memory location and an associated actual value for the first memory location; (ii) backtracking through instructions of a test case to determine the identity of a set of backtrack locations upon which the first memory location is dependent, with the set of backtrack locations being made up of at least one of: memory locations and register locations; and (iii) comparing respective simulation values and actual values for at least one of the backtrack locations to help determine a cause of the miscompare at the first memory location.Type: GrantFiled: December 27, 2013Date of Patent: May 10, 2016Assignee: International Business Machines CorporationInventors: Vysakh Kolassery, Gunaranjan Kurucheti, Subrat K. Panda
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Patent number: 9336078Abstract: Integrated circuits with memory elements may be provided. Integrated circuits may include memory error detection circuitry that is capable of correcting single-bit errors, correcting adjacent double-bit errors, and detecting adjacent triple-bit errors. The memory error detection circuitry may include encoding circuitry that generates parity check bits interleaved among memory data bits. The memory error detection circuitry may include decoding circuitry that is used to generate output data and error signals to indicate whether a correctable soft error or an uncorrectable soft error has been detected. The output data may be written back to the memory elements if a correctable soft error is detected. The memory error detection circuitry may be operable in a pipelined or a non-pipelined mode depending on the desired application.Type: GrantFiled: October 11, 2013Date of Patent: May 10, 2016Assignee: Altera CorporationInventors: Kostas Pagiamtzis, David Lewis
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Patent number: 9329948Abstract: An NVM controller measures cell damage for wear leveling in an NVM, thus improving performance, reliability, lifetime, and/or cost of a storage sub-system, such as an SSD. In a first aspect, the controller determines that an error reading a page of NVM was caused by cell damage and/or cell leakage. The controller reprograms and immediately reads back the page, detecting that the error was caused by cell damage if an error is detected during the immediate read. In a second aspect, the cell damage is tracked by updating cell damage counters for pages and/or blocks of NVM. In a third aspect, wear leveling is performed based at least in part upon measured cell damage for pages and/or blocks of NVM.Type: GrantFiled: September 15, 2012Date of Patent: May 3, 2016Assignee: Seagate Technology LLCInventors: Yan Li, Alexander Hubris, Hao Zhong
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Patent number: 9331715Abstract: A transmission apparatus includes an encoder that codes a data sequence with a parity check matrix, wherein the data sequence includes a final information bit sequence and virtual information bits, and outputs the final information bit sequence and a parity sequence, as LDPC codes, and a transmitter that transmits the LDPC codes as a transmission data. A column length of the parity check matrix is longer than a total length of the final information bit sequence and the parity sequence, by a length of the virtual information bits that are set to “0” and are not transmitted. The total length of the final information bit sequence and the parity sequence has a sequence length corresponding to a length from a first column to a predetermined column of the parity check matrix. The encoder generates the LDPC codes by using the first column to the predetermined column among one or more column(s) of the parity check matrix.Type: GrantFiled: September 21, 2015Date of Patent: May 3, 2016Assignee: Panasonic CorporationInventors: Yutaka Murakami, Shutai Okamura, Masayuki Orihashi, Takaaki Kishigami, Shozo Okasaka
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Patent number: 9329933Abstract: Methods and systems are disclosed for imminent read failure detection based upon changes in error voltage windows for non-volatile memory (NVM) cells. In certain embodiments, data stored within an array of NVM cells is checked at a first time using a diagnostic mode and high/low read voltage sweeps to determine a first error voltage window where high/low uncorrectable errors are detected. Stored data is then checked at a second time using the diagnostic mode and high/low read voltage sweeps to determine a second error voltage window where high/low uncorrectable errors are detected. The difference between the error voltage windows are then compared against a voltage difference threshold value to determine whether or not to indicate an imminent read failure condition. An address sequencer, error correction code (ECC) logic, and a bias generator can be used to implement the imminent failure detection.Type: GrantFiled: April 25, 2014Date of Patent: May 3, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Jon W. Weilemann, II, Richard K. Eguchi
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Patent number: 9329921Abstract: Methods and systems are disclosed for imminent read failure detection using high/low read voltage levels. In certain embodiments, data stored within an array of non-volatile memory (NVM) cells is checked using read voltage levels below and above a normal read voltage level. An imminent read failure is then indicated if errors are detected within the same address for both voltage checks. Further, data stored can be checked using read voltage levels that are incrementally decreased below and incrementally increased above a normal read voltage level. An imminent read failure is then indicated if read errors are detected within the same address for both voltage sweeps and if high/low read voltage levels triggering faults differ by less than a predetermined threshold value. An address sequencer, error correction code (ECC) logic, and a bias generator can be used to implement the imminent failure detection.Type: GrantFiled: April 25, 2014Date of Patent: May 3, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Jon W. Weilemann, II, Richard K. Eguchi
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Patent number: 9329932Abstract: Methods and systems are disclosed for imminent read failure detection based upon unacceptable wear for non-volatile memory (NVM) cells. In certain embodiments, a first failure time is recorded when a first diagnostic mode detects an uncorrectable error within the NVM cell array using a first set of read voltage levels below and above a normal read voltage level. A second failure time is recorded when a second diagnostic mode detects an uncorrectable error within the NVM cell array using a second set of read voltage levels below and above a normal read voltage level. The first and second failure times are then compared against a threshold wear time value to determine whether or not an imminent read failure is indicated. The diagnostic modes can be run separately for erased NVM cell distributions and programmed NVM cell distributions to provide separate wear rate determinations.Type: GrantFiled: April 25, 2014Date of Patent: May 3, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Jon W. Weilemann, II, Richard K. Eguchi
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Patent number: 9324371Abstract: The present invention is related to systems and methods for serial application of different decode algorithms to a processing data set. In some cases, a first data decode algorithm may be applied to a first detected output, and a second data decode algorithm may be applied to a second detected output. In such a case, the second detected output may be generated based at least in part on the result of applying the first data decode algorithm.Type: GrantFiled: July 2, 2012Date of Patent: April 26, 2016Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventor: Fan Zhang
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Patent number: 9323606Abstract: Systems and method relating generally to data processing, and more particularly to systems and methods for decoding information. Some disclosed systems include a first data decoding circuit, a second data decoding circuit, and a data output circuit. The second data decoding circuit is coupled to the first data decoding circuit and the data output circuit. The second data decoding circuit is operable to apply a finite alphabet iterative decoding algorithm to the first decoded output to yield a second decoded output.Type: GrantFiled: December 10, 2013Date of Patent: April 26, 2016Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Yequn Zhang, Yang Han, Yu Chin Fabian Lim, Shu Li, Fan Zhang, Shaohua Yang
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Patent number: 9325348Abstract: Methods and systems for correction of errors on a hardware data storage are provided. An example method for correction of errors on a hardware data storage can include receiving input data. The input data may include at least error statistics data and reliability data. The method can further include creating a set of matrices with predefined properties. The set of matrices can be created based on the input data. The set of matrices may include at least a generating matrix, a parity check matrix, and a decoding matrix. The method can continue with detecting the errors using the set of matrices. Upon detection of the errors, the method may further include correcting the errors using the set of matrices.Type: GrantFiled: April 22, 2014Date of Patent: April 26, 2016Assignee: Pronet Labs Ltd.Inventors: Vladimir V. Moroz, Sergey V. Ulyanov, Vladimir N. Dobrynin, Michail M. Slobodskih
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Patent number: 9323613Abstract: A data storage device includes a non-volatile memory. The non-volatile memory may include a first word line, a second word line, and a third word line. The second word line may be between the first word line and the third word line. The non-volatile memory may further include a first string and a second string. The first string may be adjacent to the second string. The data storage device may further include circuitry configured to store parity information at a fourth word line of the non-volatile memory. The parity information may correspond to a combination of first data associated with the first word line and the first string, second data associated with the first word line and the second string, third data associated with the third word line and the first string, and fourth data associated with the third word line and the second string.Type: GrantFiled: April 23, 2015Date of Patent: April 26, 2016Assignee: SANDISK TECHNOLOGIES INC.Inventors: Xinde Hu, Manuel Antonio D'Abreu
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Patent number: 9318222Abstract: A built-in self-test (BIST) circuit to test one or more memory blocks on an integrated circuit. The one or more memory blocks further includes a first memory block and a second memory block A built-in soft-repair controller (BISoR) is provided to soft repair the one or more memory blocks. The BIST circuit in conjunction with the BISoR is configured to test and soft repair the first memory block before performing test and soft repair of the second memory block.Type: GrantFiled: December 17, 2013Date of Patent: April 19, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Devanathan Varadarajan, Raghavendra Prasad KS, Harsharaj Ellur
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Patent number: 9317353Abstract: In one embodiment, a receiver is coupled to a transmitter via an interconnect. The receiver includes a voltage margining circuit to receive non-deterministic data transmitted by the transmitter via a multi-level signaling scheme and to generate a bit error report including bit error information obtained at a plurality of margining levels. Other embodiments are described and claimed.Type: GrantFiled: December 26, 2013Date of Patent: April 19, 2016Assignee: Intel CorporationInventor: Sanjay R. Ravi
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Patent number: 9317370Abstract: A semiconductor device include: a first reception inductor pad through configured to receive data from a first transmission inductor pad; a second reception inductor pad configured to receive a clock from a second transmission inductor pad; and a data recovery unit configured to generate an output data.Type: GrantFiled: December 9, 2013Date of Patent: April 19, 2016Assignee: SK hynix Inc.Inventor: Jong Joo Shim
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Patent number: 9311206Abstract: An apparatus and method for monitoring general purpose input output, GPIO, signals at GPIO pins of a GPIO port of a system on chip, SoC. The apparatus comprises a first checksum generation unit adapted to generate a first checksum on the basis of GPIO bits stored in GPIO registers of the SoC, being connected via corresponding input output, IO, pad circuits to provide analog GPIO signals at the GPIO pins. A second checksum generation unit is adapted to generate a second checksum on the basis of the analog GPIO signals at the GPIO pins representing the GPIO bits. Checker logic is adapted to compare the first checksum generated by the first checksum generation unit with a second checksum generated by the second checksum generation unit.Type: GrantFiled: April 15, 2014Date of Patent: April 12, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Carl Culshaw, Mark Maiolani, Robert F. Moran
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Patent number: 9304851Abstract: An apparatus having one or more lookup tables and a decoder is disclosed. The lookup tables are configured to store a plurality of sets of values of log likelihood ratios. The decoder is configured to (i) receive a codeword read from a memory, (ii) receive an initial one of the sets from the lookup tables and (iii) generate read data by decoding the codeword based on the values.Type: GrantFiled: December 20, 2013Date of Patent: April 5, 2016Assignee: Seagate Technology LLCInventors: Yunxiang Wu, Zhengang Chen, Erich F. Haratsch
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Patent number: 9306602Abstract: An encoding method generates an encoded sequence by performing encoding of a given coding rate according to a predetermined parity check matrix. The predetermined parity check matrix is a first parity check matrix or a second parity check matrix. The first parity check matrix corresponds to a low-density parity check (LDPC) convolutional code using a plurality of parity check polynomials. The second parity check matrix is generated by performing at least one of row permutation and column permutation with respect to the first parity check matrix. An eth parity check polynomial that satisfies zero, of the LDPC convolutional code, is expressible by using a predetermined mathematical formula.Type: GrantFiled: May 27, 2015Date of Patent: April 5, 2016Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICAInventor: Yutaka Murakami