Abstract: Disclosed is a method for efficiently managing base station retransmission traffic of a portable Internet system, and more particularly, a management method of traffic burst retransmission that can minimize a time required to retransmit a traffic burst by enhancing a hash node connection structure of a hash table.

Abstract: In an SSD controller reading from flash memory, subsequent to failure of an initial soft-decision decoding attempt based on a nominal LLR, soft-decision re-decoding attempts are made using compensated LLR soft-decision information sets, pre-calculated at respective read-equilibrium points corresponding to mean shifts and variance change in the actual charge-state distributions of the flash memory channel. According to embodiment, soft-decision re-decoding attempts are performed without a retry read, or overlapped with one or more retry reads. By overlapping re-decoding with one or more retry reads, the probability of successful decoding increases, the need for further retry reads diminishes, and throughput is improved. The LLR compensation becomes very effective over a large number of retry reads, improving decoding reliability and achieving close to optimal bit error rates, even in the presence of large channel variation.

Abstract: A method, including factoring an order of a multiplicative group of a Galois Field to produce a first integer factor p and a second integer factor q, wherein the multiplicative group includes (2m?1) elements, m a non-negative integer, so that 2m?1=pq. The method further includes receiving an element x of the Galois Field expressible as ?(qi+j), where ? is a primitive element of the group, i is a first non-negative integer less than p, and j is a second integer less than q. An inverse or a logarithm of the element x is calculated as a function of qi and j.

Abstract: A nonvolatile memory includes a plurality of memory sets, wherein each of the memory sets includes a first memory cell suitable for storing a validity signal indicating data validity of the corresponding memory set, and second memory cells suitable for storing multi-bit data or one or more-bit defect information.

Abstract: A correctable memory error may be identified at a first address within a memory device. Based on at least the identifying, a first correctable memory error count may be updated from a first quantity to a second quantity. The second quantity may be determined to exceed or not exceed a threshold. In response to the determining, the first correctable memory error count of the second quantity may be: converted to a third quantity and reported to a host device accordingly, reported to a host device, or not reported to a host device.

Abstract: A method includes encoding, in accordance with a dispersed storage error encoding function, a data segment of a data object to produce a set of encoded data slices. The method further includes creating a subset of encoded data slices, wherein the subset of encoded data slices includes less than the decode threshold number of encoded data slices. The method further includes creating one or more partial encoded data slices representing one or more encoded data slices of the set of encoded data slices that are not within the subset of encoded data slices based on the dispersed storage error encoding function and at least some of the encoded data slices of the subset of encoded data slices. The method further includes outputting the subset of encoded data slices to storage units of the DSN and outputting the one or more partial encoded data slices to another device of the DSN.

Abstract: The present application includes apparatuses and methods for determining soft data. A number of embodiments include determining soft data associated with a data state of a memory cell. In a number of embodiments, the soft data may be determined by performing a single stepped sense operation on the memory cell.

Abstract: This disclosure relates to avoiding a hard error in memory during write time by shifting data to be programmed to memory to mask the hard error. In one implementation, a method of programming data to a memory array includes obtaining error data corresponding to a selected memory cell, shifting a data pattern such that a value to be stored by the selected memory cell matches a value associated with a hard error, and programming the shifted data pattern to memory array such that the value programmed to the selected memory cell matches the value associated with the hard error.

Abstract: Forward Error Correction (FEC) techniques that generate independently decodable resource blocks are beneficial for Successive Interference Cancellation (SIC) demodulation. One FEC technique for generating independently decodable resource blocks includes mapping locally decodable FEC codeblocks into unique resource blocks such that substantially all of the bits of the FEC codeblock are carried within a single resource block. The locally decodable FEC codeblocks can be generated from different FEC encoding modules or from a common FEC encoding module. Another technique for generating independently decodable resource blocks includes encoding a stream of information bits into low-density parity-check (LDPC) codeblocks having high ratios of inward peering parity bits. These high ratios of inward peering parity bits allow substantial portions of each LDPC codeblock to be decoded independently from information carried by other LDPC codeblocks.

Abstract: A methodology and circuits for integrated circuit design are provided. A first electronic design file for an integrated circuit is provided. The first electronic design file for the integrated circuit has a timing measurement circuit thereon. Based on the first electronic design file, a number of integrated circuits are manufactured. These manufactured integrated circuits have respective timing measurement circuits arranged at predetermined locations thereon. The timing measurement circuits are used to measure a number of respective timing delay values, which are subject to manufacturing variation, on the integrated circuits. The measured timing delay values are used to set how an auto-place and route tool arranges blocks in a second electronic design file, which is routed after the timing delay values are measured, to account for any measured manufacturing variation.

Abstract: A computer implemented method for dynamic data rate adjustment within a cascaded forward error correction FEC for optical communications includes subjecting data communicated over an optical network to a forward error correction in an encoding or decoding of the data, the encoding or decoding employing a codeword, re-encoding part of the codeword for generating a subsequent codeword where an actual code rate is tuned by adjusting a size of data encoded to provide re-encoded data, and dynamically changing the re-encoded data size to achieve cascaded rate adaptive FEC for communication of the data over the optical network.

Abstract: Apparatuses and methods for memory testing with data compression is described. An example apparatus includes a plurality of latch test circuits, wherein each of the plurality of latch test circuits is coupled to a corresponding global data line of a memory. Each of the latch test circuits is configured to receive test data and is configured to latch data from the corresponding global data line or a corresponding mask bit. Each of the plurality of latch test circuits is further configured to output data based at least in part on the corresponding mask bit. A comparison circuit is coupled to an output of each of the latch test circuits and is configured to compare output data provided by each of the latch test circuits and provide a comparator output having a logical value indicative of whether all the output data matches.

Abstract: The invention relates to an apparatus for transfer of data elements between a bus controller, such as a CPU, and a memory controller. An address translator is arranged to receive a write address from the CPU, to modify the write address and to send the modified write address to the memory controller. An ECC calculator is arranged to receive write input data associated with the write address, from the CPU, and to generate an error correction code on the basis of the write input data. A concatenator is arranged to receive the write input data from the CPU, and to receive the error correction code from the ECC calculator, and to concatenate the write input data and the error correction code to obtain write output data, and to send the write output data to the memory controller.

Abstract: A memory controller is equipped with multiple error correction circuits for different complexity levels of errors, but requested data is initially sent to a requesting unit (e.g., processor) via a bypass path which provides the lowest memory latency. The requesting unit performs error detection and, if an error is found, sends a retry select signal to the memory controller. The retry select signal provides an indication of which error correction unit should be used to provide complete correction of the error but add the minimum latency necessary. On the retry transmission, the controller uses the particular error correction unit indicated by the retry select signal. The memory controller can also have a persistent error detection circuit which identifies an address as being defective when an error is repeatedly indicated by multiple retry select signals, and the control logic can automatically transmits the requested data using the appropriate error correction unit.

Abstract: Methods and apparatus are provided for sampling an indicator of the internal state of an embedded system or integrated circuit, where the indicator is sampled in a manner synchronous to the internal clock of the embedded system or integrated circuit. The resulting samples can be used for determining secret data within the embedded system or integrated circuit, detecting failures, or detecting counterfeit devices.

Abstract: A data access method for a rewritable non-volatile memory module is provided. The method includes: filling dummy data to first data in order to generate second data, and writing the second data and an error checking and correcting code (ECC code) corresponding to the second data into a first physical programming unit. The method also includes: reading data stream from the first physical programming unit, wherein the data stream includes third data and the ECC code. The method further includes: adjusting the third data according to a pattern of the dummy data in order to generate fourth data when the third data cannot be corrected by using the ECC code, and using the ECC code to correct the fourth data in order to obtain corrected data, wherein the corrected data is identical to the second data.

Abstract: A system includes a non-volatile random access memory (NVRAM) device and controller logic that detects a bad block within the device, retires the bad block and replaces the bad block with a replacement block by assigning the address of the bad block to the replacement block.

Abstract: Systems and methods for self-checking a direct memory access system are disclosed. These may include generating a check sum value associated with a first job of the plurality of jobs, the first job comprising a read job; if a first predetermined check value is available, comparing the first check sum value with the first predetermined check value; generating a second check sum value associated with a last job of the plurality of jobs, the last job comprising a write job; if a second predetermined check value is available, comparing the second check sum value with the second predetermined check value; and if the second predetermined check value is not available, comparing the first check sum value with the second check sum value.

Abstract: A method for managing operation of a logic component is provided, with the logic component including a majority vote circuit and an odd number of flip-flops equal to at least three. The method includes, following a normal operating mode of the logic component, placing a flip-flop in a test mode, and injecting a test signal into a test input of the flip-flop being tested while a logic state of the other flip-flops is frozen. A test signal output is analyzed. At the end of the test, the logic component is placed back in the normal operating mode. The majority vote circuit restores a value of the output signal from the logic component that existed prior to initiation of the test.

Abstract: The present disclosure illustrates a BCH decoding method and a decoder thereof. In this BCH decoding method, the BCH decoder receives an encode data at first, then calculates a syndrome of the encode data. After calculating the syndrome of the encode data, the BCH decoder calculates at least one error location of the encode data in response to the syndrome. Next, the BCH decoder detects at least one determining bit which a first bit string of the encode data comprises. The determining bit is configured for operatively determining whether to continue decoding the encode data. Finally, when the determining bit is detected, an error correction is then performed based upon the error location, such that the BCH decoder outputs decode data.