Abstract: A display panel and a display device are provided. The display panel includes a display region, a hole-digging region, and a boundary region disposed between the display region and the hole-digging region. The display panel also includes an array substrate and a light-emitting function layer. The array substrate includes a dam structure disposed between the display region and the boundary region. The light-emitting function layer covers the array substrate, and includes a first light-emitting component disposed over the display region and a second light-emitting component disposed over the boundary region. The array substrate further includes a base substrate and a driving device layer, and the driving device layer includes a first thin-film transistor device layer and a boundary driving circuit layer.

Abstract: Light-emitting devices and methods of making the same are described whereby lenses of any array include a material with a higher refractive index than an encapsulation layer of a substrate layer, the refractive index of the material being in a range of greater than 1.7 to 1.9 at 400 nm. The material forming the lenses includes nanocomposite comprised of inorganic nanocrystals and a polymeric matrix, wherein the nanocrystals are selected from the group consisting of ZrO2, ZnO, MgO, HfO2, NbO5, Ta2O5 and Y2O3. A 3-4 micron thick sample of the nanocomposite has an optical transmittance of at least 80% over a range of 440 nm to 800 nm.

Abstract: A device includes a first substrate formed of a first material that exhibits a threshold level of thermal conductivity. The threshold level of thermal conductivity is achieved at a cryogenic temperature range in which a quantum circuit operates. In an embodiment, the device also includes a second substrate disposed in a recess of the first substrate, the second substrate formed of a second material that exhibits a second threshold level of thermal conductivity. The second threshold level of thermal conductivity is achieved at a cryogenic temperature range in which a quantum circuit operates. In an embodiment, at least one qubit is disposed on the second substrate. In an embodiment, the device also includes a transmission line configured to carry a microwave signal between the first substrate and the second substrate.

Abstract: The disclosure relates to a thin film transistor structure, an array substrate, and a method for manufacturing a thin film transistor structure. The thin-film transistor structure includes a base substrate, a thin film transistor on the base substrate. Wherein the thin film transistor includes an active layer and a source/drain electrode on a side, facing towards the base substrate, of the active layer. Wherein the source/drain electrode has a protrusion protruding from an edge portion of the active layer in a direction parallel to a surface of the base substrate.

Abstract: A semiconductor layer stack includes a first conductive layer, a dielectric layer including a high-k material, which is formed on the first conductive layer, a second conductive layer formed on the dielectric layer, and an interface control layer formed between the dielectric layer and the second conductive layer and including a leakage blocking material, a dopant material, a high bandgap material and a high work function material.

Abstract: A device includes a fin extending from a semiconductor substrate, a gate stack over and along a sidewall of the fin, an isolation region surrounding the gate stack, an epitaxial source/drain region in the fin and adjacent the gate stack, and a source/drain contact extending through the isolation region, including a first silicide region in the epitaxial source/drain region, the first silicide region including NiSi2, a second silicide region on the first silicide region, the second silicide region including TiSix, and a conductive material on the second silicide region.

Abstract: A method of fabricating a semiconductor structure includes providing an engineered substrate including a polycrystalline substrate, a barrier layer encapsulating the polycrystalline substrate, and a bonding layer coupled to the barrier layer. The method further includes forming a first silicon layer coupled to the bonding layer, forming a dielectric layer coupled to the first silicon layer, forming a second silicon layer coupled to the dielectric layer, removing a portion of the second silicon layer and a corresponding portion of the dielectric layer to expose a portion of the first silicon layer, forming a gallium nitride (GaN) layer coupled to the exposed portion of the first silicon layer, forming a gallium nitride (GaN) based device coupled to the GaN layer, and forming a silicon-based device coupled to a remaining portion of the second silicon layer.

Abstract: A method for manufacturing an interconnect structure includes providing a substrate structure comprising a substrate, a first dielectric layer on the substrate, and a metal interconnect line formed in the first dielectric layer and extending through to a surface of the substrate; removing a portion of the first dielectric layer on opposite sides of the metal interconnect line to expose a surface of the metal interconnect line and to form a recess; forming a graphene layer on the exposed surface of the metal interconnect line; and forming a second dielectric layer filling the recess and covering the graphene layer. The interconnect structure can prevent metal atoms of the metal interconnect line from diffusion into the first and second dielectric layers.

Abstract: A quantum device with spin qubits, comprising: a semiconductor portion arranged on a buried dielectric layer of a semiconductor-on-insulator substrate also including a semiconductor support layer, wherein first distinct parts each form a confinement region of one of the qubits and are spaced apart from one another by a second part forming a coupling region between the confinement regions of the qubits; front gates each at least partially covering one of the first parts of the semiconductor portion; and wherein the support layer comprises a doped region a part of which is arranged in line with the second part of the semiconductor portion and is self-aligned with respect to the front gates, and forms a back gate controlling the coupling between the confinement regions of the qubits.

Abstract: A storage element including a storage layer configured to hold information by use of a magnetization state of a magnetic material, with a pinned magnetization layer being provided on one side of the storage layer, with a tunnel insulation layer, and with the direction of magnetization of the storage layer being changed through injection of spin polarized electrons by passing a current in the lamination direction, so as to record information in the storage layer, wherein a spin barrier layer configured to restrain diffusion of the spin polarized electrons is provided on the side, opposite to the pinned magnetization layer, of the storage layer; and the spin barrier layer includes at least one material selected from the group composing of oxides, nitrides, and fluorides.

Abstract: A layer of a crystal of a nitride of a group 13 element selected from gallium nitride, aluminum nitride, indium nitride and the mixed crystals thereof includes an upper surface and a bottom surface. The upper surface includes a linear high-luminance light-emitting part and a low-luminance light-emitting region adjacent to the high-luminance light-emitting part, and the high-luminance light-emitting part has a portion extending along an m-plane of the crystal of the nitride of the group 13 element, when the upper surface is observed by cathode luminescence. The upper surface has an arithmetic average roughness Ra of 0.05 nm or more and 1.0 nm or less.

Abstract: Metal-Oxide-Semiconductor (MOS) controlled semiconductor devices and methods of making the devices are provided. The devices include a gate which controls current flow through channel regions positioned between source/emitter and drain regions of the device. The devices include a gate oxide layer having a variable thickness. The thickness of the gate oxide layer under the edge of the gate and over the source/emitter regions is different than the thickness over the channel regions of the device. The oxide layer thickness near the edge of the gate can be greater than the oxide layer thickness over the channel regions. The source/emitter regions can be implanted to provide enhanced oxide growth during gate oxide formation. The source/emitter region can include regions that are implanted to provide enhanced oxide growth during gate oxide formation and regions which do not provide enhanced oxide growth during gate oxide formation. The devices can be SiC devices such as SiC MOSFETs and SiC IGBTs.

Abstract: A semiconductor device type of field effect transistor (FET) primarily made of nitride semiconductor materials is disclosed. The FET includes a nitride semiconductor stack providing primary and auxiliary active regions and an inactive region surrounding the active regions; electrodes of a source, a drain, and a gate; an insulating film covering the electrodes and the semiconductor stack; and a field plate on the insulating film. A feature of the FET of the invention is that the field plate is electrically in contact with the auxiliary active region through the opening provided in the insulating film.

Abstract: A method of manufacturing a nitride semiconductor light-emitting element configured to emit deep ultraviolet light includes: providing a semiconductor structure comprising: an n-side semiconductor layer comprising an n-side contact layer comprising aluminum, gallium, and nitrogen, a p-side semiconductor layer, and an active layer between the n-side semiconductor layer and the p-side semiconductor layer; forming an n-side electrode, which comprises forming, successively from an n-side contact layer side: a first layer located above the n-side contact layer and comprising a titanium layer, a second layer located above the first layer and comprising a silicon-containing aluminum alloy layer, and a third layer located above the second layer and comprising a tantalum layer and/or a tungsten layer; and heating the n-side electrode.

Abstract: A semiconductor structure includes a substrate; a first die, disposed over the substrate, wherein the first die includes a first die dielectric layer, and a first die substrate disposed on the first die dielectric layer; a second die, disposed over the first die and vertically overlapping the first die; an inter-die structure, disposed between and separating the first die and the second die; and a first through via, penetrating the first die substrate and protruding from a top surface and a bottom surface of the first die substrate, wherein a top of the first through via is disposed in the inter-die structure and a bottom of the first through via is disposed in the first die dielectric layer.

Abstract: A thin film transistor, a manufacturing method of the same, and a CMOS inverter are provided. The thin film transistor includes a base substrate, a dielectric layer, and a semiconductor layer. A first channel is provided between the source and the drain. Carbon nanotubes are provided in the first channel. A second channel is provided between the drain and the gate. An ion gel is provided in the second channel. By regulating a composition of the ion gel and a content of a dopant, a threshold voltage of a carbon nanotube thin film transistor is effectively controlled.

Abstract: A method of controlling threshold voltage shift that includes forming a first set of channel semiconductor regions on a first portion of a substrate, and forming a second set of channel semiconductor regions on a second portion of the substrate. A gate structure is formed on the first set of channel semiconductor regions and the second set of channel, wherein the gate structure extends from a first portion of the substrate over an isolation region to a second portion of the substrate. A gate cut region is formed in the gate structure over the isolation region. An oxygen scavenging metal containing layer is formed on sidewalls of the gate cut region.

Abstract: A display panel has a nanoscaled moth-eye pattern that is patterned and disposed on at least one layer disposed on a path along which light emitted from light-emitting diodes emerges, such that transmittance of light emerging outward from the display panel can be increased while reducing reflectance of external light. Further, an anti-reflector is disposed on an area other than a light-emitting area, and the moth-eye pattern is disposed on open areas of the anti-reflector. Thereby, it is possible to suppress reflected light and prevent reflection of external light on an area on which the anti-reflector cannot be disposed.

Abstract: A semiconductor device includes. A first epi-layer and a second epi-layer are each located in a first region of the semiconductor device. A first dielectric fin is located between the first epi-layer and the second epi-layer. The first dielectric fin has a first dielectric constant. A third epi-layer and a fourth epi-layer are each located in a second region of the semiconductor device. A second dielectric fin is located between the third epi-layer and the fourth epi-layer. The second dielectric fin has a second dielectric constant that is less than the first dielectric constant.

Abstract: A silicon carbide semiconductor device includes an insulated-gate electrode structure that is formed inside a gate trench that goes through a base region and reaches a upper portion of a current transport layer to control a primary current flowing through the base region; a current suppression layer of the second conductivity type embedded within an upper portion of the current transport layer; a control electrode isolation insulating film filled into a control electrode isolation trench that goes through the base region and reaches an upper portion of the current suppression layer; and a control electrode pad disposed on the control electrode isolation insulating film, wherein an upper portion of the current suppression layer abuts a sidewall of the control electrode isolation insulating film, and a lower portion of the current suppression layer covers at least bottom corners of the control electrode isolation insulating film.