Abstract: One illustrative integrated circuit (IC) product disclosed herein includes a first conductive source/drain contact structure of a first transistor with an insulating source/drain cap positioned above at least a portion of an upper surface of the first conductive source/drain contact structure and a gate-to-source/drain (GSD) contact structure that is conductively coupled to the first conductive source/drain contact structure and a first gate structure of a second transistor. In this example, the product also includes a gate contact structure that is conductively coupled to a second gate structure of a third transistor, wherein an upper surface of each of the GSD contact structure and the gate contact structure is positioned at a first level that is at a level that is above a level of an upper surface of the insulating source/drain cap.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device pertain to a semiconductor device having a channel pattern, wherein the channel pattern includes a pipe channel and vertical channels protruding in a first direction from the pipe channel. The semiconductor device also has interlayer insulating layers disposed over the pipe channel and gate electrodes disposed over the pipe channel, wherein the gate electrodes are alternately stacked with the interlayer insulating layers in the first direction, wherein the stacked interlayer insulating layers and gate electrodes surround the vertical channels, and wherein the gate electrodes include a first conductive pattern and second conductive patterns. The semiconductor device further has an etch stop pattern disposed over the first conductive pattern and under the second conductive patterns.

Abstract: A method of manufacturing a semiconductor device includes forming an interlayer insulating film over a main surface of a semiconductor substrate, forming a first conductive film pattern for a first pad and a second conductive film pattern for a second pad over the interlayer insulating film, forming an insulating film over the interlayer insulating film such that the insulating film covers the first and the second conductive film patterns, forming a first opening portion for the first pad, the first opening portion exposing a portion of the first conductive film pattern, and a second opening portion for the second pad, the second opening portion exposing a portion of the second conductive film pattern, in the insulating film, and forming a first plated layer by plating over the portion of the first conductive film pattern exposed in the first opening portion, and a second plated layer.

Abstract: A drift layer and a source region have a first conductivity type. A base region has a second conductivity type. A first trench penetrates the source region and the base region. A gate electrode is provided in the first trench through a gate insulation film. A first relaxation region is disposed below the first trench, and has the second conductivity type. A source pad electrode is electrically connected to the first relaxation region. A gate pad electrode is disposed in a non-element region. An impurity region is disposed in the non-element region, is provided on the drift layer, and has the first conductivity type. A second trench penetrates the impurity region. A second relaxation region is disposed below the second trench, and has the second conductivity type.

Abstract: A method of forming a capacitive micromachined ultrasonic transducer (CMUT) device includes bonding a CMUT substrate to a silicon on insulator (SOI) substrate. The CMUT substrate has a first thickness and the SOI substrate includes a handle, a buried oxide layer, and a device layer. At least one of the CMUT substrate or the SOI substrate includes a patterned dielectric layer. The device layer is bonded to the patterned dielectric layer to form a plurality of sealed cavities and the device layer forms a diaphragm of the plurality of cavities. The method further includes reducing the first thickness of the CMUT substrate to a second thickness and forming a plurality of through-silicon vias from a second surface of the CMUT substrate opposite the first surface.

Abstract: The invention describes an LED lighting arrangement comprising a single-layer carrier comprising a mounting surface, a metal core, and a dielectric layer between the mounting surface and the metal core; at least one LED string comprising a plurality of series-connected LED die packages mounted on the mounting surface, wherein the LED die packages of a string are arranged in a two-dimensional array comprising at least two rows; and at least one micro-via extending through the dielectric layer of the single-layer carrier and arranged to electrically connect the final cathode of an LED string to the metal core of the single-layer carrier. The invention further describes a lighting unit; and a method of manufacturing an LED lighting arrangement.

Abstract: A novel material is provided. A composite oxide semiconductor in which a first region and a plurality of second regions are mixed is provided. Note that the first region contains at least indium, an element M (the element M is one or more of Al, Ga, Y, and Sn), and zinc, and the plurality of second regions contain indium and zinc. Since the plurality of second regions have a higher concentration of indium than the first region, the plurality of second regions have a higher conductivity than the first region. An end portion of one of the plurality of second regions overlaps with an end portion of another one of the plurality of second regions. The plurality of second regions are three-dimensionally surrounded with the first region.

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a lower portion of a stack, that will comprise vertically-alternating first tiers and second tiers, on a substrate. The stack comprises laterally-spaced memory-block regions. Material of the first tiers is of different composition from material of the second tiers. Horizontally-elongated lines are formed in a lowest first tier and that are individually between immediately-laterally-adjacent of the memory-block regions. The lines comprise sacrificial material of different composition from the first-tier material that is or will be formed above the lowest first tier and from the second-tier material that is or will be formed above the lowest first tier. The vertically-alternating first tiers and second tiers of an upper portion of the stack are formed above the lower portion and the lines.

Abstract: A light-emitting device includes a substrate comprising a base member, a first wiring, a second wiring, and a via hole; at least one light-emitting element electrically connected to and disposed on the first wiring; and a covering member having light reflectivity and covering a lateral surface of the light-emitting element and a front surface of the substrate. The base member defines a plurality of depressed portions separated from the via hole in a front view and opening on a back surface and a bottom surface of the base member. The substrate includes a third wiring covering at least one of inner walls of the plurality of depressed portions and electrically connected to the second wiring. A depth of each of the plurality of depressed portions defined from the back surface toward the front surface is larger on a bottom surface side than on an upper surface side of the base member.

Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a substrate and a first fin and a second fin formed over the substrate. The semiconductor structure further includes a first anti-punch through region formed in the first fin and a second anti-punch through region formed in the second fin and first nanostructures formed over the first fin and second nanostructures formed over the second fin. The semiconductor structure further includes a barrier layer formed over the second anti-punch through region and a first gate formed around the first nanostructures. The semiconductor structure further includes a second gate formed around the second nanostructures. In addition, an interface between the barrier layer and the second anti-punch through region is higher than an interface between the first anti-punch through region and the first gate.

Abstract: The disclosure provides an OLED device and a manufacturing method thereof to improve structures of conventional OLED devices. Auxiliary cathodes are manufactured on spacers instead of a cathode layer. As a result, widths of the auxiliary cathodes may be precisely controlled, IR drop can be reduced, and quality of the OLED device can be prevented from being affected because of an overly wide auxiliary cathode.

Abstract: The field-effect mobility and reliability of a transistor including an oxide semiconductor film are improved. Provided is a semiconductor device including an oxide semiconductor film. The semiconductor device includes a first insulating film, an oxide semiconductor film over the first insulating film, a second insulating film and a third insulating film over the oxide semiconductor film, and a gate electrode over the second insulating film. The second insulating film comprises a silicon oxynitride film. When excess oxygen is added to the second insulating film by oxygen plasma treatment, oxygen can be efficiently supplied to the oxide semiconductor film.

Abstract: A method of forming a semiconductor device includes forming an ILD structure over a source/drain region, forming a source/drain contact in the ILD structure and over the source/drain region, removing a portion of the source/drain contact such that a hole is formed in the ILD structure and over a remaining portion of the source/drain contact, forming a hole liner lining a sidewall of the hole after removing the portion of the source/drain contact, and forming a conductive structure in the hole.

Abstract: A MEMS transducing apparatus includes a substrate, a conductive pad, a stacked structure of a transducing device, a first polymer layer, a second polymer layer and a third polymer layer. An upper cavity is formed through the substrate. The conductive pad is formed on a first surface of the substrate to cover a first opening of the upper cavity. The stacked structure of the transducing device is formed on the conductive pad. The first polymer layer is formed on the first surface of the substrate. A lower cavity is formed through the first polymer layer. The stacked structure of the transducing device is exposed within the lower cavity. The third polymer layer is formed on a second surface of the substrate to cover a second opening of the upper cavity. The second polymer layer is formed on the first polymer layer to cover a third opening of the lower cavity.

Abstract: A display device including a base layer including a thin film transistor, a pixel definition layer including an opening, first to third organic light emitting elements each including a first electrode, a second electrode, and a light emitting layer therebetween, an encapsulation member including a first inorganic layer covering the organic light emitting elements, a second inorganic layer disposed thereon, a first color conversion pattern disposed between the inorganic layers and overlapping the first organic light emitting element, and a second color conversion pattern disposed between the inorganic layers and overlapping the second organic light emitting element, and first and second color filter patterns having different colors from each other and overlapping the first and second color conversion patterns, respectively, in which colors of light emitted from the first and second color conversion patterns are substantially the same as colors of the first and second color filter patterns, respectively.

Abstract: A pixel definition layer for defining a light emitting device, an array substrate and a display panel are provided. The pixel definition layer includes a plurality of recessed parts, each of the plurality of recessed parts includes a bottom and an entire sidewall extending upwards from the bottom; and at least one of the plurality of recessed parts has the entire sidewall provided with a position-limiting structure.

Abstract: A method for manufacturing a MEMS sensor. The method includes: providing a substrate, applying a support layer onto a back side of the substrate, forming at least one cavity in the substrate in such a way that an access to the back side from the front side is formed, introducing a MEMS structure into the at least one cavity, and fixing the MEMS structure on the support layer.

Abstract: A method of manufacturing a semiconductor device includes: forming one or more transistor cells in a first region of a semiconductor substrate, the semiconductor substrate having a second region that is devoid of transistor cells; forming a first dielectric material over the first and second regions; forming a second dielectric material over the first dielectric material; forming a pn diode in the first dielectric material over the second region; etching first contact grooves into a p-type region of the pn diode, second contact grooves into an n-type region of the pn diode, and third contact grooves into the first region of the semiconductor substrate at the same time using a common contact formation process; and filling the first contact grooves, the second contact grooves and the third contact grooves with an electrically conductive material.

Abstract: A semiconductor device includes: a protruding conductive structure that protrudes to a height from a first surface of the semiconductor device; and a first passivation layer, the first passivation layer overlaying the protruding conductive structure by a first thickness, the first passivation layer overlaying the first surface by a second thickness greater than the first thickness, wherein the first passivation layer is planar at a top surface over the first thickness and the second thickness.

Abstract: A device is described for protecting components, housings and the like against liquids and for ventilating the same, including at least one first layer, the first layer being configured as a diaphragm and this has a first area in such a way that the first area is configured as gas-permeable and liquid-tight below a first liquid pressure, and at least one second layer, the second layer being connected pressure-tight at least in part to the first layer, and having a second area that is configured in such a way that the first area and the second area interact for sealing against a liquid at a liquid pressure greater than or equal to the first liquid pressure.