Patents Examined by Samuel Park
  • Stacked-die image sensors with shielding
    Patent number: 11133346
    Abstract: A stacked-die image sensor may be provided with an array of image pixels. The stacked-die image sensor may include at least first and second integrated circuit dies stacked on top of one another. Some of the pixel circuitry in each pixel may be formed in the first integrated circuit die and some of the pixel circuitry in each pixel may be formed in the second integrated circuit die. Coupling structures such as conductive pads may electrically couple the pixel circuitry in the first integrated circuit die to the pixel circuitry in the second integrated circuit die. A shielding structure may partially or completely surround each conductive pad to reduce parasitic capacitive coupling between adjacent conductive pads. The shielding structure may be a metal wire coupled to a ground voltage. The shielding structure may extend between columns of image pixels and/or between rows of image pixels.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: September 28, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Raminda Madurawe, Richard Mauritzson
  • Magnetic storage device
    Patent number: 11133456
    Abstract: According to one embodiment, a magnetic storage device includes: a magnetoresistive effect element including a non-magnet, and a stacked structure on the non-magnet, the stacked structure including: a first ferromagnet on the non-magnet; an anti-ferromagnet being exchange-coupled with the first ferromagnet; and a second ferromagnet between the first ferromagnet and the anti-ferromagnet. The stacked structure is configured to: have a first resistance value in response to a first current flowing through the stacked structure in a first direction, and have a second resistance value different from the first resistance value in response to a second current flowing through the stacked structure in a second direction opposite to the first direction.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: September 28, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takeshi Iwasaki, Akiyuki Murayama, Tadashi Kai, Tadaomi Daibou, Masaki Endo, Shumpei Omine, Taichi Igarashi, Junichi Ito
  • Staggered-type tunneling field effect transistor
    Patent number: 11133183
    Abstract: The disclosure describes a tunneling field effect transistor having an overlapping structure between the source and drain regions providing a greater tunneling area. The source or drain region may be a doped region in a semi-conductive substrate. The other source or drain region may be formed by epitaxial deposition over the doped region. The gate is formed over the epitaxial region where the doped and epitaxial regions overlap. The doped region may be formed in a fin structure with the epitaxial region and gate being formed on the top and sides of the fin.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: September 28, 2021
    Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Chiao Tung University
    Inventors: Steve S. Chung, E. Ray Hsieh, Kuan-Yu Chang
  • Method for improving wire bonding strength of an image sensor
    Patent number: 11133275
    Abstract: A method for manufacturing a bond pad structure includes providing a substrate structure including a substrate, a first metal layer on the substrate, and a passivation layer on the first metal layer, the passivation layer having an opening extending to the first metal layer; and filling the opening of the passivation layer with a second metal layer. The bond pad structure has a significantly increased thickness compared with the thickness of the exposed portion of the first metal layer in the opening, thereby ensuring wire bonding reliability and yield.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: September 28, 2021
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Yunlong Kong
  • Embedded bridge substrate having an integral device
    Patent number: 11133256
    Abstract: Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate; a bridge, embedded in the package substrate, wherein the bridge includes an integral passive component, and wherein a surface of the bridge include first contacts in a first interconnect area and second contacts in a second interconnect area; a first die coupled to the passive component via the first contacts in the first interconnect area; and a second die coupled to the second contacts in the second interconnect area.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: September 28, 2021
    Assignee: Intel Corporation
    Inventors: Amit Kumar Jain, Sameer Shekhar, Chin Lee Kuan, Kevin Joseph Doran, Dong-Ho Han
  • Staggered-type tunneling field effect transistor
    Patent number: 11133184
    Abstract: The disclosure describes a tunneling field effect transistor having an overlapping structure between the source and drain regions providing a greater tunneling area. The source or drain region may be a doped region in a semi-conductive substrate. The other source or drain region may be formed by epitaxial deposition over the doped region. The gate is formed over the epitaxial region where the doped and epitaxial regions overlap. The doped region may be formed in a fin structure with the epitaxial region and gate being formed on the top and sides of the fin.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: September 28, 2021
    Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Chiao Tung University
    Inventors: Steve S. Chung, E. Ray Hsieh, Kuan-Yu Chang
  • Staggered-type tunneling field effect transistor
    Patent number: 11133182
    Abstract: The disclosure describes a tunneling field effect transistor having an overlapping structure between the source and drain regions providing a greater tunneling area. The source or drain region may be a doped region in a semi-conductive substrate. The other source or drain region may be formed by epitaxial deposition over the doped region. The gate is formed over the epitaxial region where the doped and epitaxial regions overlap. The doped region may be formed in a fin structure with the epitaxial region and gate being formed on the top and sides of the fin.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: September 28, 2021
    Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Chiao Tung University
    Inventors: Steve S. Chung, E. Ray Hsieh, Kuan-Yu Chang
  • Semiconductor device and method of manufacturing thereof
    Patent number: 11133326
    Abstract: In a semiconductor device including a plurality of memory regions formed of split-gate type MONOS memories, threshold voltages of memory cells are set to different values for each memory region. Memory cells having different threshold voltages are formed by forming a metal film, which is a work function film constituting a memory gate electrode of a memory cell in a data region, and a metal film, which is a work function film constituting a memory gate electrode of a memory cell in a code region, of different materials or different thicknesses.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: September 28, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Naoki Takizawa, Tomoya Saito
  • Semiconductor device and fabrication method thereof
    Patent number: 11049973
    Abstract: Semiconductor device and fabrication method are provided. The method includes providing a substrate with a fin including a plurality of channel layers and a sacrificial layer; forming a dummy gate structure across the fin; forming first grooves in the fin on two sides of the dummy gate structure; forming a first protection layer on sidewalls of the first channel layer and the dummy gate structure; forming second grooves by etching the fin at bottoms of the first grooves; removing a portion of sidewalls of the initial second channel layer to form a second channel layer; removing the first protection layer; forming a doped source/drain layer in the first grooves and the second grooves; forming a dielectric layer over the substrate and the fin; removing the dummy gate structure and the sacrificial layers to form a gate opening; and forming a gate structure in the gate opening.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: June 29, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fei Zhou
  • High-resistance memory devices
    Patent number: 11043535
    Abstract: Cross bar array devices and methods of forming the same include first electrodes arranged adjacent to each other and extending in a first direction. Second electrodes are arranged transversely to the first electrodes. An electrolyte layer is disposed between the first electrodes and the second electrodes, the electrolyte layer comprising a nitridated dielectric material.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: June 22, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Marwan H. Khater, Seyoung Kim, Hiroyuki Miyazoe, Vijay Narayanan
  • Semiconductor crystal substrate, infrared detector, method for producing semiconductor crystal substrate, and method for producing infrared detector
    Patent number: 11043517
    Abstract: A semiconductor crystal substrate includes a crystal substrate that is formed of a material including one of GaSb and InAs, a first buffer layer that is formed on the crystal substrate and formed of a material including GaSb, and a second buffer layer that is formed on the first buffer layer and formed of a material including GaSb. The first buffer layer has a p-type conductivity, and the second buffer layer has an n-type conductivity.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: June 22, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Shigekazu Okumura, Shuichi Tomabechi, Ryo Suzuki
  • Singulation and bonding methods and structures formed thereby
    Patent number: 11037904
    Abstract: Methods of singulation and bonding, as well as structures formed thereby, are disclosed. A method includes singulating a first chip and after the singulating the first chip, bonding the first chip to a second chip. The first chip includes a first semiconductor substrate and a first interconnect structure on a front side of the first semiconductor substrate. The singulating the first chip includes etching through a back side of the first semiconductor substrate through the first interconnect structure.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: June 15, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Semiconductor devices including liners, and related systems
    Patent number: 11038107
    Abstract: A semiconductor structure includes a plurality of stack structures overlying a substrate. Each stack structure includes a first chalcogenide material over a conductive material overlying the substrate, an electrode over the first chalcogenide material, a second chalcogenide material over the electrode, a liner on sidewalls of at least one of the first chalcogenide material or the second chalcogenide material, and a dielectric material over and in contact with sidewalls of the electrode and in contact with the liner. Related semiconductor devices and systems, methods of forming the semiconductor structure, semiconductor device, and systems, and methods of forming the liner in situ are disclosed.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: June 15, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Dale W. Collins, Andrea Gotti, F. Daniel Gealy, Tuman E. Allen, Swapnil Lengade
  • Semiconductor device and method of making a semiconductor device
    Patent number: 11011446
    Abstract: A semiconductor device and a method of making the same. The device includes a semiconductor substrate having a major surface, a backside and side surfaces extending between the major surface and the backside. The semiconductor device also includes at least one metal layer extending across the backside of the substrate. A peripheral part of the at least one metal layer located at the edge of the substrate between the backside and at least one of the side surfaces extends towards a plane containing the major surface. This can prevent burrs located at the peripheral part of the at least one metal layer interfering with the mounting of the backside of the substrate on the surface of a carrier.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: May 18, 2021
    Assignee: NEXPERIA B.V.
    Inventors: Tonny Kamphuis, Leo van Gemert, Hans van Rijckevorsel, Sascha Moeller, Hartmut Buenning, Steffen Holland, Y Kuang Huang
  • High voltage device and manufacturing method thereof
    Patent number: 10998404
    Abstract: A high voltage device includes: a semiconductor layer, an isolation structure, a first deep well, a second deep well, a drift well, a first well, a second well, a body region, a body contact, a high voltage well, a gate, and a source and a drain. The high voltage well is formed in the second deep well, and the high voltage well is not in contact with any of the first deep well, the first well, and the second well, wherein at least part of the high voltage well is located right below all of a drift region to suppress a latch-up current generated in the high voltage device.
    Type: Grant
    Filed: July 4, 2019
    Date of Patent: May 4, 2021
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventor: Tsung-Yi Huang
  • Three-dimensional cross-point memory device containing inter-level connection structures and method of making the same
    Patent number: 10991761
    Abstract: First electrically conductive lines, first pillar structures, second electrically conductive lines, second pillar structures, third electrically conductive lines, third pillar structures, fourth electrically conductive lines, and fourth pillar structures are formed over a substrate. Each pillar structure includes a memory element. Interconnection structures are formed on the first electrically conductive lines. The first electrically conductive lines may have thinned segments located outside the area of the arrays of memory elements, and the interconnection structures may be formed on the thinned segments. Alternatively or additionally, the interconnection structures may include a vertical stack of a first conductive via structure contacting a respective one of the first electrically conductive lines, a conductive pad structure, and a second conductive via structure.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: April 27, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yuji Takahashi, Wei Kuo Shih
  • Reducing loss in stacked quantum devices
    Patent number: 10978425
    Abstract: The proposed device includes a first chip (102) comprising a superconducting quantum bit and a second chip (104) bonded to the first chip, the second chip including a substrate (108) having first and second opposing surfaces. The first surface (101) facing the first chip includes a layer (105) of superconductor material which includes a first circuit element. The second chip further includes a second layer (107) on the second surface (103) which includes a second circuit element, and a through connector (109) that extends from the first surface to the second surface and electrically connects a portion of the superconductor material layer to the second circuit element.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: April 13, 2021
    Assignee: Google LLC
    Inventor: Theodore Charles White
  • Interconnections for a substrate associated with a backside reveal
    Patent number: 10957661
    Abstract: An apparatus relating generally to a substrate is disclosed. In this apparatus, a post extends from the substrate. The post includes a conductor member. An upper portion of the post extends above an upper surface of the substrate. An exterior surface of the post associated with the upper portion is in contact with a dielectric layer. The dielectric layer is disposed on the upper surface of the substrate and adjacent to the post to provide a dielectric collar for the post. An exterior surface of the dielectric collar is in contact with a conductor layer. The conductor layer is disposed adjacent to the dielectric collar to provide a metal collar for the post, where a top surface of each of the conductor member, the dielectric collar and the metal collar have formed thereon a bond structure for interconnection of the metal collar and the conductor member.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: March 23, 2021
    Assignee: Invensas Corporation
    Inventor: Cyprian Emeka Uzoh
  • Light receiving element and method of manufacturing the same
    Patent number: 10950744
    Abstract: A light receiving element is obtained by: forming a first mask having a first opening and a second opening; performing etching by using the first mask, to allow the etching to progress at a higher rate in the second opening than in the first opening; forming a second mask having a third opening and a fourth opening; performing etching by using the second mask, to form a mesa in a region interposed by the third opening, and an n-type contact region in the fourth opening; and forming a first electrode on the mesa and a second electrode on the n-type contact region, the first electrode being electrically connected to the third layer, the second electrode being electrically connected to the first layer, wherein a region covered with the first mask and exposed through the fourth opening of the second mask turns into the n-type contact region after the etching using the second mask.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: March 16, 2021
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Daisuke Kimura, Sundararajan Balasekaran
  • 3D memory with confined cell
    Patent number: 10937832
    Abstract: A plurality of memory cells in a cross-point array in which the memory cell stacks in the cross-points include a switch element, a conductive barrier layer, and a confined cell structure in series, and having sides aligned within the cross-point area of the corresponding cross-point, the confined cell structure including surfactant spacers within the cross-point area having outside surfaces on a pair of opposing sides of the stack, and a body of programmable resistance memory material confined between inside surfaces of the surfactant spacers. The memory cells can be operated as multi-level cells in a 3D array.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: March 2, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Erh-Kun Lai, Hsiang-Lan Lung