Patents Examined by Samuel Park
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Patent number: 11133275Abstract: A method for manufacturing a bond pad structure includes providing a substrate structure including a substrate, a first metal layer on the substrate, and a passivation layer on the first metal layer, the passivation layer having an opening extending to the first metal layer; and filling the opening of the passivation layer with a second metal layer. The bond pad structure has a significantly increased thickness compared with the thickness of the exposed portion of the first metal layer in the opening, thereby ensuring wire bonding reliability and yield.Type: GrantFiled: July 28, 2017Date of Patent: September 28, 2021Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATIONInventor: Yunlong Kong
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Patent number: 11133256Abstract: Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate; a bridge, embedded in the package substrate, wherein the bridge includes an integral passive component, and wherein a surface of the bridge include first contacts in a first interconnect area and second contacts in a second interconnect area; a first die coupled to the passive component via the first contacts in the first interconnect area; and a second die coupled to the second contacts in the second interconnect area.Type: GrantFiled: June 20, 2019Date of Patent: September 28, 2021Assignee: Intel CorporationInventors: Amit Kumar Jain, Sameer Shekhar, Chin Lee Kuan, Kevin Joseph Doran, Dong-Ho Han
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Patent number: 11133184Abstract: The disclosure describes a tunneling field effect transistor having an overlapping structure between the source and drain regions providing a greater tunneling area. The source or drain region may be a doped region in a semi-conductive substrate. The other source or drain region may be formed by epitaxial deposition over the doped region. The gate is formed over the epitaxial region where the doped and epitaxial regions overlap. The doped region may be formed in a fin structure with the epitaxial region and gate being formed on the top and sides of the fin.Type: GrantFiled: October 7, 2019Date of Patent: September 28, 2021Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Chiao Tung UniversityInventors: Steve S. Chung, E. Ray Hsieh, Kuan-Yu Chang
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Patent number: 11133182Abstract: The disclosure describes a tunneling field effect transistor having an overlapping structure between the source and drain regions providing a greater tunneling area. The source or drain region may be a doped region in a semi-conductive substrate. The other source or drain region may be formed by epitaxial deposition over the doped region. The gate is formed over the epitaxial region where the doped and epitaxial regions overlap. The doped region may be formed in a fin structure with the epitaxial region and gate being formed on the top and sides of the fin.Type: GrantFiled: September 26, 2019Date of Patent: September 28, 2021Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Chiao Tung UniversityInventors: Steve S. Chung, E. Ray Hsieh, Kuan-Yu Chang
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Patent number: 11133326Abstract: In a semiconductor device including a plurality of memory regions formed of split-gate type MONOS memories, threshold voltages of memory cells are set to different values for each memory region. Memory cells having different threshold voltages are formed by forming a metal film, which is a work function film constituting a memory gate electrode of a memory cell in a data region, and a metal film, which is a work function film constituting a memory gate electrode of a memory cell in a code region, of different materials or different thicknesses.Type: GrantFiled: May 13, 2019Date of Patent: September 28, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Naoki Takizawa, Tomoya Saito
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Patent number: 11049973Abstract: Semiconductor device and fabrication method are provided. The method includes providing a substrate with a fin including a plurality of channel layers and a sacrificial layer; forming a dummy gate structure across the fin; forming first grooves in the fin on two sides of the dummy gate structure; forming a first protection layer on sidewalls of the first channel layer and the dummy gate structure; forming second grooves by etching the fin at bottoms of the first grooves; removing a portion of sidewalls of the initial second channel layer to form a second channel layer; removing the first protection layer; forming a doped source/drain layer in the first grooves and the second grooves; forming a dielectric layer over the substrate and the fin; removing the dummy gate structure and the sacrificial layers to form a gate opening; and forming a gate structure in the gate opening.Type: GrantFiled: September 4, 2019Date of Patent: June 29, 2021Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventor: Fei Zhou
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Patent number: 11043535Abstract: Cross bar array devices and methods of forming the same include first electrodes arranged adjacent to each other and extending in a first direction. Second electrodes are arranged transversely to the first electrodes. An electrolyte layer is disposed between the first electrodes and the second electrodes, the electrolyte layer comprising a nitridated dielectric material.Type: GrantFiled: January 12, 2017Date of Patent: June 22, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Takashi Ando, Marwan H. Khater, Seyoung Kim, Hiroyuki Miyazoe, Vijay Narayanan
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Patent number: 11043517Abstract: A semiconductor crystal substrate includes a crystal substrate that is formed of a material including one of GaSb and InAs, a first buffer layer that is formed on the crystal substrate and formed of a material including GaSb, and a second buffer layer that is formed on the first buffer layer and formed of a material including GaSb. The first buffer layer has a p-type conductivity, and the second buffer layer has an n-type conductivity.Type: GrantFiled: June 4, 2020Date of Patent: June 22, 2021Assignee: FUJITSU LIMITEDInventors: Shigekazu Okumura, Shuichi Tomabechi, Ryo Suzuki
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Patent number: 11037904Abstract: Methods of singulation and bonding, as well as structures formed thereby, are disclosed. A method includes singulating a first chip and after the singulating the first chip, bonding the first chip to a second chip. The first chip includes a first semiconductor substrate and a first interconnect structure on a front side of the first semiconductor substrate. The singulating the first chip includes etching through a back side of the first semiconductor substrate through the first interconnect structure.Type: GrantFiled: November 24, 2015Date of Patent: June 15, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Tsang-Jiuh Wu, Wen-Chih Chiou
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Patent number: 11038107Abstract: A semiconductor structure includes a plurality of stack structures overlying a substrate. Each stack structure includes a first chalcogenide material over a conductive material overlying the substrate, an electrode over the first chalcogenide material, a second chalcogenide material over the electrode, a liner on sidewalls of at least one of the first chalcogenide material or the second chalcogenide material, and a dielectric material over and in contact with sidewalls of the electrode and in contact with the liner. Related semiconductor devices and systems, methods of forming the semiconductor structure, semiconductor device, and systems, and methods of forming the liner in situ are disclosed.Type: GrantFiled: November 28, 2018Date of Patent: June 15, 2021Assignee: Micron Technology, Inc.Inventors: Dale W. Collins, Andrea Gotti, F. Daniel Gealy, Tuman E. Allen, Swapnil Lengade
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Patent number: 11011446Abstract: A semiconductor device and a method of making the same. The device includes a semiconductor substrate having a major surface, a backside and side surfaces extending between the major surface and the backside. The semiconductor device also includes at least one metal layer extending across the backside of the substrate. A peripheral part of the at least one metal layer located at the edge of the substrate between the backside and at least one of the side surfaces extends towards a plane containing the major surface. This can prevent burrs located at the peripheral part of the at least one metal layer interfering with the mounting of the backside of the substrate on the surface of a carrier.Type: GrantFiled: November 3, 2016Date of Patent: May 18, 2021Assignee: NEXPERIA B.V.Inventors: Tonny Kamphuis, Leo van Gemert, Hans van Rijckevorsel, Sascha Moeller, Hartmut Buenning, Steffen Holland, Y Kuang Huang
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Patent number: 10998404Abstract: A high voltage device includes: a semiconductor layer, an isolation structure, a first deep well, a second deep well, a drift well, a first well, a second well, a body region, a body contact, a high voltage well, a gate, and a source and a drain. The high voltage well is formed in the second deep well, and the high voltage well is not in contact with any of the first deep well, the first well, and the second well, wherein at least part of the high voltage well is located right below all of a drift region to suppress a latch-up current generated in the high voltage device.Type: GrantFiled: July 4, 2019Date of Patent: May 4, 2021Assignee: RICHTEK TECHNOLOGY CORPORATIONInventor: Tsung-Yi Huang
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Patent number: 10991761Abstract: First electrically conductive lines, first pillar structures, second electrically conductive lines, second pillar structures, third electrically conductive lines, third pillar structures, fourth electrically conductive lines, and fourth pillar structures are formed over a substrate. Each pillar structure includes a memory element. Interconnection structures are formed on the first electrically conductive lines. The first electrically conductive lines may have thinned segments located outside the area of the arrays of memory elements, and the interconnection structures may be formed on the thinned segments. Alternatively or additionally, the interconnection structures may include a vertical stack of a first conductive via structure contacting a respective one of the first electrically conductive lines, a conductive pad structure, and a second conductive via structure.Type: GrantFiled: May 13, 2019Date of Patent: April 27, 2021Assignee: SANDISK TECHNOLOGIES LLCInventors: Yuji Takahashi, Wei Kuo Shih
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Patent number: 10978425Abstract: The proposed device includes a first chip (102) comprising a superconducting quantum bit and a second chip (104) bonded to the first chip, the second chip including a substrate (108) having first and second opposing surfaces. The first surface (101) facing the first chip includes a layer (105) of superconductor material which includes a first circuit element. The second chip further includes a second layer (107) on the second surface (103) which includes a second circuit element, and a through connector (109) that extends from the first surface to the second surface and electrically connects a portion of the superconductor material layer to the second circuit element.Type: GrantFiled: September 13, 2016Date of Patent: April 13, 2021Assignee: Google LLCInventor: Theodore Charles White
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Patent number: 10957661Abstract: An apparatus relating generally to a substrate is disclosed. In this apparatus, a post extends from the substrate. The post includes a conductor member. An upper portion of the post extends above an upper surface of the substrate. An exterior surface of the post associated with the upper portion is in contact with a dielectric layer. The dielectric layer is disposed on the upper surface of the substrate and adjacent to the post to provide a dielectric collar for the post. An exterior surface of the dielectric collar is in contact with a conductor layer. The conductor layer is disposed adjacent to the dielectric collar to provide a metal collar for the post, where a top surface of each of the conductor member, the dielectric collar and the metal collar have formed thereon a bond structure for interconnection of the metal collar and the conductor member.Type: GrantFiled: July 31, 2019Date of Patent: March 23, 2021Assignee: Invensas CorporationInventor: Cyprian Emeka Uzoh
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Patent number: 10950744Abstract: A light receiving element is obtained by: forming a first mask having a first opening and a second opening; performing etching by using the first mask, to allow the etching to progress at a higher rate in the second opening than in the first opening; forming a second mask having a third opening and a fourth opening; performing etching by using the second mask, to form a mesa in a region interposed by the third opening, and an n-type contact region in the fourth opening; and forming a first electrode on the mesa and a second electrode on the n-type contact region, the first electrode being electrically connected to the third layer, the second electrode being electrically connected to the first layer, wherein a region covered with the first mask and exposed through the fourth opening of the second mask turns into the n-type contact region after the etching using the second mask.Type: GrantFiled: June 5, 2019Date of Patent: March 16, 2021Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Daisuke Kimura, Sundararajan Balasekaran
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Patent number: 10937832Abstract: A plurality of memory cells in a cross-point array in which the memory cell stacks in the cross-points include a switch element, a conductive barrier layer, and a confined cell structure in series, and having sides aligned within the cross-point area of the corresponding cross-point, the confined cell structure including surfactant spacers within the cross-point area having outside surfaces on a pair of opposing sides of the stack, and a body of programmable resistance memory material confined between inside surfaces of the surfactant spacers. The memory cells can be operated as multi-level cells in a 3D array.Type: GrantFiled: June 21, 2018Date of Patent: March 2, 2021Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Erh-Kun Lai, Hsiang-Lan Lung
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Patent number: 10937696Abstract: In a method for producing a capacitor, a dielectric structure is generated in a trench of a semiconductor substrate. The dielectric structure includes a plurality of adjacent dielectric layers having opposing material tensions.Type: GrantFiled: November 24, 2015Date of Patent: March 2, 2021Assignee: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.Inventors: Florian Krach, Tobias Erlbacher
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Patent number: 10937905Abstract: A semiconductor device includes at least a first transistor including at least a second level metal layer (second metal layer) above a first level metal layer coupled by a source contact to a source region doped with a first dopant type. The second level metal layer is coupled by a drain contact to a drain region doped with the first dopant type. A gate stack is between the source region and drain region having the second level metal layer coupled by a contact thereto. The second level metal layer is coupled by a contact to a first isolation region doped with the second dopant type. The source region and drain region are within the first isolation region. A second isolation region doped with the first dopant type encloses the first isolation region, and is not coupled to the second level metal layer so that it electrically floats.Type: GrantFiled: May 23, 2014Date of Patent: March 2, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Yongxi Zhang, Philip L. Hower, Sameer P. Pendharkar, John Lin, Guru Mathur, Scott Balster, Victor Sinow
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Patent number: 10923583Abstract: The present invention relates to the technical field of power semiconductor devices, particularly to an insulated gate bipolar transistor with a MOS controllable hole path. According to the present invention, a MOS controllable gate structure formed by a gate dielectric layer, a MOS control gate electrode and a P-type MOS channel region are embedded in a P+ floating p-body region of the conventional IGBT structure. The MOS region is equivalent to a switch controlled by a gate voltage. When the device is turned on under a forward voltage, the potential of the p-body region is floated to store holes, reducing the saturation conduction voltage drop of the device. Under the condition of turn-off and short-circuit, the hole extracting path is provided and the Miller capacitance is lowered, thereby lowering the turn-off losses and enhancing the short-circuit withstand capability.Type: GrantFiled: October 15, 2019Date of Patent: February 16, 2021Assignee: UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINAInventors: Zehong Li, Xin Peng, Yishang Zhao, Min Ren, Bo Zhang
