Abstract: A method for manufacturing an opening structure is provided. The method may include: forming a patterned mask over a first side of a carrier; forming material over the first side of the carrier covering at least a portion of the carrier; forming a first opening in the carrier from a second side of the carrier opposite the first side of the carrier to at least partially expose a surface of the patterned mask; and forming a second opening in the material from the second side of the carrier using the patterned mask as a mask.

Abstract: A method for forming an interconnect structure is provided. The method for forming the interconnect structure includes forming a metal line over a substrate, forming a first dielectric layer surrounding the metal line, selectively forming a dielectric block over the first dielectric layer without forming the dielectric block on the metal line, forming a second dielectric layer over the dielectric block and the metal line, etching the second dielectric layer to form a via hole corresponding to the metal line, and filling the via hole with a conductive material.

Abstract: An integrated circuit having a body comprised of semiconducting material has one or more electronic components formed in a first region of the body and at least another electronic component formed in the second region of the body. A thermal barrier separates the two regions. By one approach that thermal barrier comprises a gap formed in the body. The gap may comprise an air gap or may be partially or wholly filled with material that inhibits thermal conduction. The thermal barrier may at least substantially surround the aforementioned second region. The second region may also include one or more temperature sensors disposed therein. A temperature control circuit may use the corresponding temperature information from within the second region to actively control the second region temperature using a temperature forcing element that is disposed at least proximal to the second region.

Abstract: A semiconductor device includes a device isolation layer provided on a substrate, the device isolation layer defining first and second sub-active patterns, first and second gate electrodes crossing the first and second sub-active patterns, respectively, and an isolation structure provided on the device isolation layer between the first and second sub-active patterns. The first and second sub-active patterns extend in a first direction and are spaced apart from each other in the first direction. The device isolation layer includes a diffusion break region disposed between the first and second sub-active patterns. The isolation structure covers a top surface of the diffusion break region.

Abstract: A memory device includes first conductive lines extending in a first direction, second conductive lines extending in a second direction, and a plurality of memory cells each arranged between the first and second conductive lines and each including a variable resistance memory layer and a switch material pattern. The switch material pattern includes an element injection area arranged in an outer area of the switch material pattern, and an internal area covered by the element injection area. The internal area contains a first content of at least one element from arsenic (As), sulfur (S), selenium (Se), and tellurium (Te), the element injection area contains a second content of the at least one element from As, S, Se, and Te, and the second content has a profile in which a content of the at least one element decreases away from the at least one surface of the switch material pattern.

Abstract: A sacrificial gate stack for forming a nanosheet transistor includes a substrate. first, second and third silicon channel nanosheets formed over the substrate, and a first sandwich of germanium (Ge) containing layers disposed between the substrate and first silicon channel nanosheet. The stack also includes a second sandwich of Ge containing layers disposed between the first silicon channel nanosheet and the second silicon channel nanosheet; and a third sandwich of Ge containing layers disposed between the second silicon channel nanosheet and the third silicon channel nanosheet. Each sandwich includes first and second low Ge containing layers surrounding a silicon germanium (SiGe) sacrificial nanosheet that has a higher Ge concentration than the first and second low Ge containing layers.

Abstract: A display device including: a display panel; a cover plate disposed on the display panel; and an adhesive layer disposed between the display panel and the cover plate, wherein the adhesive layer includes a main adhesive layer and a thin film layer, the thin film layer includes a first thin film layer and a second thin film layer disposed on the first thin film layer, the first thin film layer contains a siloxane functional group and the second thin film layer contains fluorine, and the second thin film layer is disposed between the first thin film layer and the cover plate.

Abstract: A semiconductor device includes a semiconductor element made up of a semiconductor substrate, an element electrode formed on the substrate, and a wiring layer electrically connected to the element electrode. The semiconductor device further includes a lead frame supporting the semiconductor element, a first conductive member electrically connecting the semiconductor element and the lead frame, a second conductive member overlapping with the semiconductor element as seen in plan view, and a sealing resin covering the semiconductor element, a part of the lead frame, and the first and second conductive member. The wiring layer includes a first pad portion and a second pad portion. The second conductive member has a first connecting portion bonded to the first pad portion and a second connecting portion bonded to the second pad portion.

Abstract: An light-emitting apparatus and a method for producing a light-emitting apparatus are disclosed. In an embodiment, the apparatus includes at least one organic device and an outcoupling layer, wherein the at least one organic device emits electromagnetic radiation during operation, wherein the outcoupling layer contains optical structures, and wherein the apparatus has a non-Lambertian radiation distribution curve during operation. The outcoupling layer influences the radiation passing through it in an optically varying manner by the optical structures along a lateral direction in order to produce the non-Lambertian radiation distribution curve.

Abstract: A device includes a semiconductor fin protruding from a substrate, a first gate stack over the semiconductor fin and a second gate stack over the semiconductor fin, a first source/drain region in the semiconductor fin adjacent the first gate stack and a second source/drain region in the semiconductor fin adjacent the second gate stack, a first layer of a first dielectric material on the first gate stack and a second layer of the first dielectric material on the second gate stack, a first source/drain contact on the first source/drain region and adjacent the first gate stack, a first layer of a second dielectric material on a top surface of the first source/drain contact, and a second source/drain contact on the second source/drain region and adjacent the second gate stack, wherein the top surface of the second source/drain contact is free of the second dielectric material.

Abstract: A resistive non-volatile memory cell includes a first electrode, a second electrode and an oxide layer disposed between the first electrode and the second electrode, the memory cell being capable of reversibly switching between: —a high resistance state obtained by applying a first bias voltage between the first electrode and the second electrode; and—a low resistance state obtained by applying a second bias voltage between the first electrode and the second electrode; the oxide layer including a switching zone forming a conduction path prioritised for the current passing through the memory cell when the memory cell is in the low resistance state. The oxide layer includes a first zone doped with aluminium or silicon, the aluminium or silicon being present in the first zone with an atomic concentration that is selected so as to locate the switching zone outside the first zone.

Abstract: A semiconductor chip is disclosed that includes a chip pad disposed in a first region of a chip body, a redistribution wiring test pad disposed in the first region of the chip body spaced apart from the chip pad and connected to the chip pad through a redistribution wiring structure, and a redistribution wiring connection pad disposed in the first region of the chip body or a second region of the chip body and connected to the chip pad through the redistribution wiring structure.

Abstract: One or more exemplary embodiments provide a display apparatus including a substrate; an encapsulation substrate facing the substrate; a display portion disposed between the substrate and the encapsulation substrate and including a display region; a metal layer disposed on the substrate and surrounding the display region; and a sealing portion formed to overlap the metal layer and coupling the substrate to the encapsulation substrate, wherein the metal layer includes a first region disposed outside of the display region at one side of the display region and a second region disposed outside of the display region at another side, which is opposite to the one side, of the display region, and the metal layer has a different light reflectivity in the first region and the second region.

Abstract: The inventive concepts provide a three-dimensional (3D) image sensor, based on structured light (SL), having a structure in which difficulty in a manufacturing process of a wiring layer is decreased and/or an area of a bottom pad of a capacitor is increased. The 3D image sensor includes: a pixel area including a photodiode in a semiconductor substrate and a gate group including a plurality of gates; a multiple wiring layer on an upper portion of the pixel area, the multiple wiring layer including at least two wiring layers; and a capacitor structure between a first wiring layer on a lowermost wiring layer of the multiple wiring layer and a second wiring layer on the first wiring layer, the capacitor structure including a bottom pad, a top pad, and a plurality of capacitors, wherein the bottom pad is connected to the first wiring layer.

Abstract: Electrically modulatable photodiode, comprising a substrate having a first and a second p-n junction, a common contact for jointly contacting the p or n dopings of the two p-n junctions, and two further contacts for separately contacting the other doping of the p and n dopings of the two p-n junctions, and a circuit, wherein the circuit is designed to measure a current flow caused by charge carriers which have been generated by impinging radiomagnetic waves in the substrate and which have reached the first further contact, and to switch the second further contact at different times to at least one first and one second switching state, wherein in the first switching state the second further contact is switched to the floating state and in the second switching state a potential is applied, and wherein a blocking voltage applied between the common contact and the first further contact is constant.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a circuit region, a seal ring region and an assembly isolation region. The circuit region includes a first conductive layer. The seal ring region includes a second conductive layer. The assembly isolation region is between the circuit region and the seal ring region. The first conductive layer and the second conductive layer respectively include a portion extending into the assembly isolation region thereby forming an electric component in the assembly isolation region.

Abstract: A light-emitting substrate and a repair method thereof are provided. The light-emitting substrate includes a substrate, a first conductive line, a second conductive line, a signal line, an insulating layer, first to third light-emitting devices, and a first sub-conductive line. The first and second conductive lines and the signal line are disposed on the substrate. The insulating layer is disposed on the first and second conductive lines. The first to third light-emitting devices are disposed on the substrate. The first light-emitting device is disposed corresponding to the first conductive line. The second light-emitting device is disposed corresponding to the second conductive line. The first to third light-emitting devices are disposed corresponding to the signal line. The first sub-conductive line is disposed on the insulating layer. The first sub-conductive line is overlapped with the first and second conductive lines.

Abstract: A semiconductor structure disposed on a substrate including a first metal layer disposed on the substrate, a gate insulating layer disposed on the substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopping pattern disposed on the oxide semiconductor layer, and a second metal layer disposed on the etch stopping layer. The first metal layer includes a gate line. The gate insulating layer covers the gate line. Patterning of the oxide semiconductor layer defines an oxide semiconductor pattern. The second metal layer includes a source electrode and a drain electrode electrically connected to the oxide semiconductor pattern. The etch stopping layer is located between the second metal layer and the oxide semiconductor layer. The second metal layer includes a signal line disposed on the etch stopping layer and is electrically connected to the oxide semiconductor pattern. A manufacturing method of the semiconductor structure is also provided.

Abstract: In a contact hole of an interlayer insulating film, a tungsten film forming a contact plug is embedded via a barrier metal. The interlayer insulating film is formed by sequentially stacked HTO and BPSG films. The BPSG film has an etching rate faster than that of the HTO film with respect to a hydrofluoric acid solution used in wet etching of preprocessing before formation of the barrier metal. After the contact hole is formed in the interlayer insulating film, a width of an upper portion of the contact hole at the BPSG film is increased in a step-like shape, to be wider than a width of a lower portion at the HTO film by the wet etching before the formation of the barrier metal, whereby an aspect ratio of the contact hole is reduced. Thus, size reductions and enhancement of the reliability may be realized.

Abstract: The semiconductor package including a first semiconductor package including a first semiconductor package substrate, and a first semiconductor chip on the first semiconductor package substrate, an interposer disposed on the first semiconductor package is provided. Interposer electrically connects the first semiconductor package with an external semiconductor package, and has first and second sides opposed to each other. The second side is located between the first side and the first semiconductor package substrate, a first recess is formed in the second side of the interposer. The first recess has side walls extended from the second side toward the first side of the interposer and an upper surface connected to the side walls and the upper surface of the first recess faces the first semiconductor chip and a via in the interposer. The via does not transmit an electrical signal between the first semiconductor package and the external semiconductor package.