Patents Examined by Samuel Park
  • Semiconductor structure and manufacturing method thereof
    Patent number: 11342307
    Abstract: A semiconductor structure includes a first die, a second die, and a first conductive via. The first die includes a first dielectric layer and a first landing pad embedded in the first dielectric layer. The second die includes a second dielectric layer and a second landing pad embedded in the second dielectric layer. The first die is disposed on the second die. The second landing pad has a through-hole. The first conductive via extends from the first landing pad toward the second landing pad and penetrates through the through-hole of the second landing pad.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: May 24, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Hsih-Yang Chiu, Yi-Jen Lo
  • Trench formation scheme for programmable metallization cell to prevent metal redeposit
    Patent number: 11342379
    Abstract: Some embodiments relate to a memory device. The memory device includes a top electrode overlying a bottom electrode. A data storage layer overlies the bottom electrode. The bottom electrode cups an underside of the data storage layer. The top electrode overlies the data storage layer. A top surface of the bottom electrode is aligned with a top surface of the top electrode.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: May 24, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fu-Ting Sung, Chung-Chiang Min, Yuan-Tai Tseng
  • Power flat no-lead package
    Patent number: 11342260
    Abstract: A power flat no-lead (FN) package is provided. The power FN package includes a die paddle; a die, disposed on the die paddle, operating at a radio frequency; a first lead, disposed by a first side of the die paddle, configured to receive an input signal of the power FN package; and a capacitor, disposed on the first lead; wherein a lead width of the first lead is greater than a half of a first side length of the first side.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: May 24, 2022
    Assignee: WIN Semiconductors Corp.
    Inventors: Chih-Wen Huang, Jui-Chieh Chiu
  • Display substrate and display device
    Patent number: 11335714
    Abstract: The present disclosure provides a display substrate and a display device. A display substrate provided by an embodiment of the present disclosure includes: a display region and a peripheral region surrounding the display region; the display region includes: a plurality of gate lines, a plurality of data lines, and a plurality of pixel units, and each of the plurality of pixel units includes a driving transistor and a pixel electrode that are connected to each other; the peripheral region includes: signal lines and at least one electrostatic discharge structure for performing electrostatic discharge on the signal lines.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: May 17, 2022
    Assignees: Beijing BOE Technology Development Co., Ltd., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Pan Li, Xinyin Wu, Yong Qiao
  • Display device
    Patent number: 11335737
    Abstract: A display device includes a display unit including transistors disposed in a display area and signal lines arranged in a non-display area located along an edge of the display area, at least one of the signal lines being electrically connected to the transistors; and an input sensing unit disposed over the display unit and including sensing electrodes disposed on the display area, sensing lines arranged on the non-display area, and a first dummy pattern disposed on the non-display area and spaced apart from the sensing electrodes as compared with the sensing line, wherein the first dummy pattern overlaps a first signal line of the signal lines, the first signal line being spaced farthest from the display area, a planar shape of an overlap pattern formed by overlapping the first dummy pattern and the first signal line coincides with a planar shape of an alignment mark.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: May 17, 2022
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yeon Tae Kim, Chung Yi, Young Kwan Kim, Young Soo No
  • High electron mobility transistor
    Patent number: 11322600
    Abstract: A high electron mobility transistor (HEMT) includes a buffer layer on a substrate, a barrier layer on the buffer layer, a gate electrode on the barrier layer, a first passivation layer adjacent to two sides of the gate electrode, and a p-type semiconductor layer between the gate electrode and the barrier layer. Preferably, a corner of the p-type semiconductor layer contacting a sidewall of the first passivation layer includes a first curve, and a bottom surface of the p-type semiconductor layer directly on the first passivation layer includes a second curve.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: May 3, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: An-Chi Liu, Chun-Hsien Lin
  • Display device and method for manufacturing the same
    Patent number: 11302821
    Abstract: Provided are a display device and a method for manufacturing the same. The display device includes: a connection source electrode and a connection drain electrode connected to a first source electrode a the first drain electrode, respectively by penetrating an isolation insulating layer and a second interlayer dielectric layer to enhance a characteristic of an element and reliability of the display device.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: April 12, 2022
    Assignee: LG Display Co., Ltd.
    Inventors: SoYoung Noh, YoungJang Lee, HyoJin Kim, Hyuk Ji
  • Gate resistance reduction through low-resistivity conductive layer
    Patent number: 11302818
    Abstract: A device includes a semiconductor fin, and a gate stack on sidewalls and a top surface of the semiconductor fin. The gate stack includes a high-k dielectric layer, a work-function layer overlapping a bottom portion of the high-k dielectric layer, and a blocking layer overlapping a second bottom portion of the work-function layer. A low-resistance metal layer overlaps and contacts the work-function layer and the blocking layer. The low-resistance metal layer has a resistivity value lower than second resistivity values of both of the work-function layer and the blocking layer. A gate spacer contacts a sidewall of the gate stack.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: April 12, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Chiang Wu, Po-Cheng Chen, Kuo-Chan Huang, Hung-Chin Chung, Hsien-Ming Lee, Chien-Hao Chen
  • Dynamic random access memory and method of forming the same
    Patent number: 11296091
    Abstract: Provided is a dynamic random access memory (DRAM) including a substrate, a plurality of word-line sets, a plurality of bit-line structures, a plurality of capacitors, a plurality of capacitor contacts, and a plurality of air gaps. The substrate has a plurality of active areas. The word-line sets extend along a Y direction and disposed in the substrate. The bit-line structures extend along a X direction, disposed on the substrate, and across the word-line sets. The capacitors are respectively disposed at two terminals of the active areas. The capacitor contacts are respectively disposed between the capacitors and the active regions. The air gaps are disposed in a plurality of spaces enclosed by the bit-line structures and the capacitor contacts. A method of forming a DRAM is also provided.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: April 5, 2022
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Li-Peng Chang, San-Jung Chang
  • Organic light-emitting display apparatus and manufacturing method thereof
    Patent number: 11296175
    Abstract: An improved organic light-emitting display apparatus prevents damage of wiring due to a mask during the manufacturing process, and a manufacturing method thereof. An organic light-emitting display apparatus includes a display unit formed on a substrate, a pad unit formed at one outer side of the display unit on the substrate, a wiring unit formed as a multilayer structure on the substrate to couple the display unit to the pad unit, a thin film encapsulating layer covering the display unit, and a protrusion unit that does not overlap the uppermost layer of wiring of the multilayered wiring unit.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: April 5, 2022
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yang-Wan Kim, Won-Kyu Kwak
  • Array substrate, array substrate body component, and display device
    Patent number: 11287707
    Abstract: An array substrate includes switching components, pixel electrodes connected to the switching components, a common electrode disposed to overlap the pixel electrodes via an insulator, first lines connected to the switching components, second lines connected to the switching components and extending while crossing the first lines, first protection circuits connected to the first lines, respectively, second protection circuits connected to the second lines, respectively, a first common line connected to the first lines via the first protection circuits, and a second common line connected to the second lines via the second protection circuits. The second common line is connected to the first common line directly or indirectly and not being connected to the common electrode.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: March 29, 2022
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Kazuko Yoshida, Masahiro Yoshida
  • Simultaneous dual-band image sensors
    Patent number: 11282887
    Abstract: A simultaneous dual-band image sensor having a plurality of pixels includes a substrate, a common ground on the substrate, wherein each pixel includes a Band 1 absorber layer on the common ground layer, a barrier layer on the Band 1 absorber layer, a Band 2 absorber layer on the barrier layer, a ring opening in the pixel formed by a removed portion of the Band 2 absorber layer, a removed portion of the barrier layer and a removed portion of the Band 1 absorber layer, wherein the ring opening does not extend through the Band 1 absorber layer, a first contact on a portion of the Band 2 absorber layer inside the ring, and a second contact on a portion of the Band 2 absorber layer outside the ring. The Band 1 absorber layer and the Band 2 absorber layer are n-type, or the Band 1 absorber layer and the Band 2 absorber layer are p-type.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: March 22, 2022
    Assignee: HRL Laboratories, LLC
    Inventors: Minh B. Nguyen, Brett Z. Nosho
  • Semiconductor memory device
    Patent number: 11282853
    Abstract: According to one embodiment, a semiconductor memory device includes a base layer, conductive layers, an insulation layer, a semiconductor layer and a charge storage layer. The conductive layers are stacked above the base layer in a first direction. The insulation layer is extending in the conductive layers in the first direction. The semiconductor layer is arranged between the insulation layer and the conductive layers. The charge storage layer is arranged between the semiconductor layer and the conductive layers. The insulation layer includes a first insulation layer arranged on a side of the base layer and containing polysilazane and a second insulation layer arranged on the first insulation layer on a side opposite from the base layer.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: March 22, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Shinichi Sotome, Tatsufumi Hamada, Yasuhiro Uchimura, Tomohiro Kuki
  • Semiconductor memory devices formed using selective barrier metal removal
    Patent number: 11276732
    Abstract: A method for manufacturing a semiconductor memory device includes depositing a bottom metal line layer on a dielectric layer, and patterning the bottom metal line layer into a plurality of bottom metal lines spaced apart from each other. In the method, a plurality of switching element dielectric portions are formed on respective ones of the plurality of bottom metal lines, and a top metal line layer is deposited on the plurality of switching element dielectric portions. The method further includes patterning the top metal line layer into a plurality of top metal lines spaced apart from each other. The plurality of top metal lines are oriented perpendicular to the plurality of bottom metal lines.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: March 15, 2022
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Hiroyuki Miyazoe
  • Transistor devices with source/drain regions comprising an interface layer that comprises a non-semiconductor material
    Patent number: 11264499
    Abstract: One illustrative transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate and a source region and a drain region, each of which comprise an epi cavity with a bottom surface and a side surface. The transistor further includes an interface layer positioned on at least one of the side surface and the bottom surface of the epi cavity in each of the source/drain regions, wherein the interface layer comprises a non-semiconductor material and an epi semiconductor material positioned on at least an upper surface of the interface layer in the epi cavity in each of the source region and the drain region.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: March 1, 2022
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: John J. Pekarik, Steven M. Shank, Anthony K. Stamper, Vibhor Jain, John Ellis-Monaghan
  • Power module with MOSFET body diode on which energization test can be conducted efficiently
    Patent number: 11251178
    Abstract: A power module includes a first MOS transistor and a first Schottky barrier diode for a lower arm, and a second MOS transistor and a second Schottky barrier diode for an upper arm. In one embodiment, one positive-side power supply terminal and one negative-side power supply terminal are provided, while an output terminal to which the first and second MOS transistors are connected and an output terminal to which the first and second Schottky barrier diodes are connected are provided as separate output terminals.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: February 15, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Seiya Sugimachi, Masataka Shiramizu
  • Integrated circuit with optical tunnel
    Patent number: 11239152
    Abstract: The invention relates to an integrated circuit with an active transistor area and a plurality of wiring layers arranged above the active transistor area. At least one optical device is integrated in the active transistor area. The optical device is electrically connected with at least one of the wiring layers. At least one optical tunnel extends from the at least one optical device through the plurality of wiring layers to a surface of an uppermost wiring layer of the plurality of wiring layers facing away from the active transistor area.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: February 1, 2022
    Assignee: International Business Machines Corporation
    Inventors: Otto Andreas Torreiter, Thomas Gentner, Martin Eckert
  • Structure and formation method of chip package with fan-out feature
    Patent number: 11239173
    Abstract: A package structure and a formation method of a package structure are provided. The method includes forming a redistribution structure over a carrier substrate and disposing a semiconductor die over the redistribution structure. The method also includes stacking an interposer substrate over the redistribution structure. The interposer substrate extends across edges of the semiconductor die. The method further includes disposing one or more device elements over the interposer substrate. In addition, the method includes forming a protective layer to surround the semiconductor die.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: February 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Hao Tsai, Meng-Liang Lin, Po-Yao Chuang, Techi Wong, Shin-Puu Jeng
  • Array substrate and manufacturing method thereof, display device
    Patent number: 11237441
    Abstract: The present disclosure relates to an array substrate and a manufacturing method thereof, a display device. The manufacturing method of the array substrate includes: upon manufacturing of a gate layer, connecting a gate line in the gate layer with a signal line electrically; and after manufacturing of an active layer is completed, disconnecting electrical connection of the gate line with the signal line.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: February 1, 2022
    Assignees: Hefei Xinsheng Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Xinjie Zhang, Chengwei Liu
  • Interconnect structure and method for forming the same
    Patent number: 11227833
    Abstract: A method for forming an interconnect structure is provided. The method for forming the interconnect structure includes forming a first dielectric layer over a substrate, forming a first conductive feature through the first dielectric layer, forming a first blocking layer on the first conductive feature, forming a first etching stop layer over the first dielectric layer and exposing the first blocking layer, removing at least a portion of the first blocking layer, forming a first metal bulk layer over the first etching stop layer and the first conductive feature, and etching the first metal bulk layer to form a second conductive feature electrically connected to the first conductive feature.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: January 18, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shao-Kuan Lee, Cheng-Chin Lee, Hsin-Yen Huang, Hai-Ching Chen, Shau-Lin Shue