Patents Examined by Sara Crane
  • Patent number: 6787371
    Abstract: In a method of forming a ferroelectric film according to the present invention, pulsed laser light or pulsed lamp light is applied to an amorphous oxide film formed over a substrate to form microcrystalline nuclei of oxide in the film. Crystallization of the oxide is performed by applying pulsed laser light or pulsed lamp light to the film including the microcrystalline nuclei to form the ferroelectric film.
    Type: Grant
    Filed: March 27, 2003
    Date of Patent: September 7, 2004
    Assignee: Seiko Epson Corporation
    Inventor: Tatsuo Sawasaki
  • Patent number: 6787792
    Abstract: An emitter includes an electron supply layer, a dielectric layer on the electron supply layer defining an emission area, and a filled zeolite emission layer within the defined emission area and in contact with the electron supply layer. The filled zeolite emission layer holds a semiconductor material within the cage of the zeolite.
    Type: Grant
    Filed: April 18, 2002
    Date of Patent: September 7, 2004
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Thomas Novet, David M. Schut
  • Patent number: 6784016
    Abstract: The present invention relates to an organic light emitting device (OLED) for producing electroluminescence having, in order, for example, an anode, a hole transporting layer (HTL), a blocking layer, an electron transporting layer (ETL), and a cathode. In the devices of the present invention, the hole transporting layer comprises a polymeric material, which material may be emissive or may be doped with an emissive dopant. The blocking layer and the electron transporting layer are small-molecule materials. The presence of a blocking layer confines the emission of light to the polymer layer, which may be a HTL or a separate emitting layer (EL). The devices of the present invention are suitable for use in single color, multi-color and full-color, passive or active matrix OLED displays.
    Type: Grant
    Filed: June 21, 2002
    Date of Patent: August 31, 2004
    Assignee: The Trustees of Princeton University
    Inventors: Ke Long, James C. Sturm, Min-Hao Michael Lu
  • Patent number: 6784452
    Abstract: An organic TFT including an organic film, first and second electrodes each disposed in contact with opposite surfaces of the organic film each other; and a third electrode disposed at a specified distance from each of the first and second electrodes, the third electrode being applied with a voltage to control current flowing from one of the first and the second electrodes to the other through the organic film; and the organic film including a compound represented by general formula [1]. In this TFT, the carrier moves from one of the first and the second electrodes to the other in the direction of the film thickness of the organic film. The device structure realizes the enough short channel length. The organic film provides the higher mobility, thereby the organic TFT with the sufficiently higher speed response is realized.
    Type: Grant
    Filed: October 4, 2002
    Date of Patent: August 31, 2004
    Assignee: NEC Corporation
    Inventors: Satoru Toguchi, Atsushi Oda, Hitoshi Ishikawa
  • Patent number: 6781149
    Abstract: An organic light-emitting device with improved performance including an anode formed over a substrate; a light-emitting layer formed over the anode for producing light in response to hole-electron recombination; and a performance-enhancing layer formed over the light-emitting layer including one or more chemical reducing materials selected to improve the performance of the organic light-emitting device. The device also includes an electron-transporting layer formed over the performance-enhancing layer, and a cathode formed over the electron-transporting layer.
    Type: Grant
    Filed: February 14, 2003
    Date of Patent: August 24, 2004
    Assignee: Eastman Kodak Company
    Inventors: Liang-Sheng Liao, Joseph K. Madathil, Kevin P. Klubek, Dustin L. Comfort, Ching W. Tang
  • Patent number: 6780745
    Abstract: An IC chip comprises a chip peripheral portion and a core macro portion. The chip peripheral portion is made up of a plurality of I/O buffers each of which serves as an interface between the IC chip and the outside thereof, and a plurality of pads to which bonding wires are electrically connected. A CPU core block, peripheral blocks, random logic blocks, and a gate array block are placed in the core macro portion. The respective blocks are electrically connected to one another by metal interconnections. The gate array block designed by a gate array system is layout-designed in accordance with a standard cell system or full custom system together with other blocks.
    Type: Grant
    Filed: August 20, 1999
    Date of Patent: August 24, 2004
    Assignee: Oki Electric Industry Co. Ltd.
    Inventors: Kimikatsu Shoji, Hirofumi Tadokoro, Osamu Yanaga
  • Patent number: 6781212
    Abstract: A selectively doped trench isolation device is provided. The trench isolation device of the preferred embodiment includes a semiconductor substrate having a trench. A thin field oxide layer is grown on the side walls of the trench, and the trench is filled with a heavily doped polysilicon. The work function difference between the substrate and the heavily doped polysilicon increases the field threshold voltage of the gated trench isolation device so that smaller isolation structures can be formed between adjacent active devices in higher density integrated circuits.
    Type: Grant
    Filed: August 31, 1998
    Date of Patent: August 24, 2004
    Assignee: Micron Technology, Inc
    Inventors: David Y. Kao, Rongsheng Yang
  • Patent number: 6777714
    Abstract: Concave and convex are formed on the substrate 1, the amorphous silicon layer 4 is formed on the metallic catalyst 3 dispersed and arranged in a dotted shape in the concave portion of the concave and convex, the crystal phases 5 having respective orientations from the metallic catalyst 3 are grown, further the crystal phases 5 are integrated with each other by continuing heat treatment and the polycrystalline silicon layer 6 is formed. A crystalline silicon semiconductor device and its method for fabrication which are costly advantageous and capable of efficiently forming the polycrystalline silicon layer of a predetermined thickness needed as a semiconductor device are provided.
    Type: Grant
    Filed: February 9, 2001
    Date of Patent: August 17, 2004
    Assignee: Hitachi Cable, Ltd.
    Inventors: Shinichi Muramatsu, Yasushi Minagawa, Fumihito Oka, Susumu Takahashi, Yoshiaki Yazawa
  • Patent number: 6777744
    Abstract: A method and structure for an improved, vertically configured inverter array is provided. The inverter includes a buried gate contact coupling the body regions of a complementary pair of transistors. An electrical contact couples the second source/drain regions of the complementary pair of transistors. The transistors are formed in vertical pillars of single crystalline semiconductor material.
    Type: Grant
    Filed: June 4, 2001
    Date of Patent: August 17, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Wendell P. Noble
  • Patent number: 6773946
    Abstract: Disclosed is a nanosized III-nitride compound semiconductor multiple quantum well light-emitting diode, comprising a silicon substrate (100), and an amorphous silicon nitride layer (base) (200) formed on the substrate and including III-nitride compound semiconductor nano grains (230) spontaneously formed therein. The nanosized nitride semiconductor multiple quantum well light-emitting diode and the fabrication method thereof according to the present invention are free from the problems of the conventional III-nitride compound semiconductor epitaxial thin film growth on silicon substrates. Accordingly, a high-quality nanosized III-nitride compound semiconductor multiple quantum well light-emitting diode having no crystalline defect can be provided.
    Type: Grant
    Filed: December 30, 2002
    Date of Patent: August 10, 2004
    Assignee: Kwagju Institute of Science and Technology
    Inventors: Yong Tae Moon, Nae Man Park, Baek Hyun Kim, Seong Ju Park
  • Patent number: 6774406
    Abstract: A light emitting diode device has a body having a recess. The body comprises a pair of half bodies made of metal and an insulation layer is provided between the half bodies. An LED is provided on a bottom of the recess. The LED is coated with a transparent coloring resin including a fluorescent material. The recess is covered by a transparent sealing plate.
    Type: Grant
    Filed: November 25, 2002
    Date of Patent: August 10, 2004
    Assignee: Citizen Electronics Co., Ltd.
    Inventor: Hiroto Isoda
  • Patent number: 6774402
    Abstract: A pn-junction type compound semiconductor light-emitting device having a substrate formed of a crystal, a first barrier layer provided on the substrate and formed of an undoped boron phosphide-base semiconductor of first conduction type, and a light-emitting layer of a first or a second conduction type provided on the first barrier layer including a plurality of superposed constituent layers formed of group III nitride semiconductors each having a different band gap. The constituent layer of the light-emitting layer provided closest to the first barrier layer is a first light-emitting constituent layer formed of a group III nitride semiconductor containing phosphorus (P). A method for producing the semiconductor light-emitting device is also disclosed.
    Type: Grant
    Filed: March 11, 2003
    Date of Patent: August 10, 2004
    Assignee: Showa Denko Kabushiki Kaisha
    Inventor: Takashi Udagawa
  • Patent number: 6774392
    Abstract: An organic light emitting diode (OLED) includes a substrate having a first electrode layer formed thereon in a predetermined pattern, an insulator layer defining the upper portion of the substrate having the first electrode layer in a predetermined pattern, an organic polymer layer formed based on the pattern defined by the insulator layer, a barrier for blocking flow of the organic polymer layer at both ends of the pattern defined by the insulator layer, and a second electrode layer formed on the organic polymer layer.
    Type: Grant
    Filed: December 12, 2002
    Date of Patent: August 10, 2004
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Werner Humbs, Albrecht Uhlig, Marcus Schadig
  • Patent number: 6770558
    Abstract: Methods and apparatus for forming and/or enabling interconnection in a substrate. An example embodiment of a method comprises forming a via in the substrate. A preconditioning layer is deposited on the substrate. A catalyst layer is then bound to the preconditioning layer. A conductive material is deposited on the catalyst layer by electro-less deposition to fill the via with the conductive material. Deposition of the conductive material is selectively disabled from coating surfaces of the substrate outside the via. Advantageous alternatives are presented.
    Type: Grant
    Filed: February 21, 2003
    Date of Patent: August 3, 2004
    Assignee: International Business Machines Corporation
    Inventors: Emmanuel Delamarche, Michel Despont, Ute Drechsler, Matthias Geissler
  • Patent number: 6770914
    Abstract: A III nitride semiconductor substrate for ELO is provided for forming a III nitride film whose surface is controlled independent of the film's thickness. A III nitride underlayer including at least Al is directly formed on a base made of e.g. a sapphire single crystal, and not formed through a buffer layer formed at a low temperature. After that patterns made of e.g SiO2 are formed on the underlayer.
    Type: Grant
    Filed: June 5, 2002
    Date of Patent: August 3, 2004
    Assignee: NGK Insulators, Ltd.
    Inventors: Tomohiko Shibata, Keiichiro Asai, Shigeaki Sumiya, Mitsuhiro Tanaka
  • Patent number: 6770498
    Abstract: The present invention is to provide a process for fabricating light emitting diode (LED) packages. The process begins with a first step of providing a platelike frame having a plurality of cells, each of which is composed of a main plate and a separate arm. Secondly, an LED die and a reflecting ring are respectively mounted on a top surface of each main plate such that the die is located at a center of the reflecting ring. Next, connect a conductive wire between a top surface of the die and a top surface of the separate arm by wire bonding technique. And then, mold a domed transparent encapsulant on each of the cells. The encapsulant encapsulates the die, the reflecting ring and the conductive wire and covers the main plate and the separate arm, and fills a space between the main plate and the separate arm to remain their spaced apart. Finally, cut the frame according to the size of each cell, and then LED packages are obtained.
    Type: Grant
    Filed: October 4, 2002
    Date of Patent: August 3, 2004
    Assignees: Lingsen Precision Industries, Ltd., Cotco Holdings Ltd.
    Inventor: Cheng-Hsiang Hsu
  • Patent number: 6765237
    Abstract: A light source including a specific LED and phosphor combination capable of emitting white light for direct illumination. In one embodiment, the light source includes an LED chip emitting in the 380-420 nm range radiationally coupled to a phosphor blend first phosphor selected from the group consisting of (Sr,Ba,Ca,Mg)5(PO4)3Cl:Eu2+ (SECA) and BaMg2Al16O27:Eu2+ with a second phosphor having the formula (Tb1-x-yAxREy)3DzO12 (TAG), where A is a member selected from the group consisting of Y, La, Gd, and Sm; RE is a member selected from the group consisting of Ce, Pr, Nd, Sm, Eu, Gd, Dy, Ho, Er, Tm, Yb, and Lu; D is a member selected from the group consisting of Al, Ga, and In; x is in the range from 0 to about 0.5, y is in the range from about 0 to about 0.2, and z is in the range from about 4 to about 5. The light source thus produced will provide a high quality white light.
    Type: Grant
    Filed: January 15, 2003
    Date of Patent: July 20, 2004
    Assignee: GELcore, LLC
    Inventors: Daniel Darcy Doxsee, Cherian Jacob
  • Patent number: 6765234
    Abstract: A semiconductor light emitting device includes: a silicon substrate; and a plurality of column-shaped multilayered structures formed on the silicon substrate in such a manner that the column-shaped multilayered structures are insulated from one another, the column-shaped multilayered structures being made of a nitride semiconductor material, and each column-shaped multilayered structure including a light emitting layer, wherein the column-shaped multilayered structures are connected to one another by an electrode.
    Type: Grant
    Filed: December 21, 2001
    Date of Patent: July 20, 2004
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Norikatsu Koide
  • Patent number: 6765244
    Abstract: A III nitride multilayer including a given substrate, a III nitride underfilm including an Al content of 50 atomic percent or more for all of the III elements present in the III nitride underfilm, and a III nitride film including a lower Al content than the Al content of the III nitride underfilm by 10 atomic percent or more. A full width at half maximum X-ray rocking curve value of the III nitride film is set to 800 seconds or below at the (100) plane. A full width at half maximum X-ray rocking curve value of the III nitride film is set to 200 seconds or below at the (002) plane.
    Type: Grant
    Filed: May 28, 2002
    Date of Patent: July 20, 2004
    Assignee: NGK Insulators, Ltd.
    Inventors: Tomohiko Shibata, Shigeaki Sumiya, Keiichiro Asai, Mitsuhiro Tanaka
  • Patent number: 6762450
    Abstract: A method of forming a capacitor includes, a) providing a node to which electrical connection to a first capacitor plate is to be made; b) then, providing a finned lower capacitor plate in ohmic electrical connection with the node using no more than one photomasking step; and c) providing a capacitor dielectric layer and a conductive second capacitor plate layer over the conductive layer.
    Type: Grant
    Filed: June 6, 2001
    Date of Patent: July 13, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej Sandhu, Pierre C. Fazan