Abstract: A supported glass substrate is placed with an element-forming surface thereof facing downward. A mother sealing substrate is placed on a support made of a quartz glass or the like. An ultraviolet-curing sealing resin is applied on the mother sealing substrate. After the glass substrate is aligned with the mother sealing substrate, the glass substrate is pressed toward the sealing substrate. The sealing resin is irradiated with ultraviolet light transmitted through the sealing substrate.

Abstract: An electrical switching device includes a semiconductor having a channel therein which is proximate to at least on channel tap in an extension region and also to a gate. A conductor (e.g., a metal) is disposed proximate to the extension region but is electrically isolated from both the extension region and the gate (e.g., through the use of one or more insulators). The conductor has a workfunction outside of the bandgap of a semiconductor in the extension region and therefore includes a layer of charge in the extension region. The magnitude and polarity of this layer of charge is controlled through selection of the metal, the semiconductor, and the insulator.

Abstract: A compound tetrahedrally coordinated semiconductor structure, whose chemical formula is generally of the form IInIIImIVlVpVIq, where n, m, l, p, q represent the relative abundance of each element associated with a particular group of the periodic table. The flexibility of the chemical formula may be used to adjust the lattice constant and polarity to eliminate mismatches from substrates. Other properties, such as those of band gaps, can also be tuned. The design is amenable to layer-by-layer heteroepitaxial growth. In exemplary embodiments, a structure is provided that matches lattice constant and polarity with a Si(100) surface, while having a direct band gap of 1.59 ?m.

Abstract: Heightening of breakdown voltage of a trench gate type power MISFET is actualized without increasing the number of manufacturing steps. In the manufacturing method of the semiconductor device according to the present invention, p? type semiconductor region and p? type field limiting rings are formed in a gate line area simultaneously in one impurity ion implantation step so as to bring them into contact with a groove having a gate extraction electrode formed therein. Upon formation, supposing that the width of the gate extraction electrode disposed outside the groove is CHSP, and the resistivity of the n? type single crystal silicon layer 1B is ? (?·cm), the CHSP is set to satisfy the following equation: CHSP?3.80+0.148 ?.

Abstract: An organic semiconductor device is provided. The device has a first electrode and a second electrode, with an organic semiconductor layer disposed between the first and second electrodes. An electrically conductive grid is disposed within the organic semiconductor layer, which has openings in which the organic semiconductor layer is present. At least one insulating layer is disposed adjacent to the electrically conductive grid, preferably such that the electrically conductive grid is completely separated from the organic semiconductor layer by the insulating layer. Methods of fabricating the device, and the electrically conductive grid in particular, are also provided. In one method, openings are formed in an electrically conductive layer with a patterned die, which is then removed. In another method, an electrically conductive layer and a first insulating layer are etched through the mask to expose portions of a first electrode.

Abstract: An embodiment of the invention includes a routing architecture with a plurality of predesigned layers and a custom layer. The structure includes a plurality of parallel vertical tracks. In one layer, the tracks include a pin coupled to an input/output of an underlying function block and the track also includes a first portion of an unbroken conductive path. A second portion of the unbroken conductive path is formed under the pin in at least a second predesigned layer. In some embodiments, the second portion of the unbroken conductive path is formed in the second predesigned layer for some tracks and a third predesigned layer for other tracks. Hence, pins and unbroken conductive paths are multiplexed in a single track. In addition, the second predesigned layer further includes long horizontal conductors.

Abstract: Disclosed is an electroluminescent device comprising a light emitting layer comprising a boron complex wherein the boron is bonded to a nitrogen atom of a 6-membered heteroaromatic ring group and to a nitrogen atom of a 5-membered heteroaromatic ring group, provided that the 5- and 6-membered heteroaromatic ring groups are further connected by a methene bridge, and provided further that the 5-membered heteroaromatic ring contains at least one additional heteroatom that is divalent or trivalent. Also disclosed is a device containing the electroluminescent device and a process for emitting light using the device.

Abstract: A method fabricates ICs in which organic semiconductor crystallites serve as active channels of semiconductor devices. The method includes providing a substrate with a surface that has a preselected pattern of adhesion sites located thereon. The adhesion sites are prepared to adhere crystallites of an organic semiconductor. The method also includes applying a plurality of crystallites of the organic semiconductor to the surface to enable a portion of the applied crystallites to adhere at the prepared adhesion sites.

Abstract: The light extraction efficiency of a Light Emitting Diode (LED) is improved by providing pits etched into a top, emitting, surface of the LED. The presence of the pits reduces the mean distance to a sidewall in active regions, and creates regions of higher transmission at which a semi-transparent contact is not present. The walls of the pits are preferably coated with a passivating layer, such as silicon dioxide, to reduce surface leakage currents and to improve the operational stability of the device at the expense of a reduction in optical extraction efficiency commonly obtained with encapsulants having a higher index of refraction.

Abstract: A compound represented by the following formula (II): wherein L12 represents one of a from 2- to 6-valent connecting group having a heteroaryl group and a from 2- to 6-valent connecting group comprising a non-conjugate connecting group having an arylene group; n2 represents an integer of from 2 to 6; R represents one of an alkyl group having from 1 to 20 carbon atoms, an aryl group having from 6 to 20 carbon atoms, a heteroaryl group having from 2 to 20 carbon atoms and a silyl group having from 3 to 20 carbon atoms; and m represents an integer of from 0 to 6.

Abstract: An undercoat layer inclusive of a metal nitride layer is formed on a substrate. Group III nitride compound semiconductor layers are formed on the undercoat layer continuously.

Abstract: An organic field effect transistor utilizes a bifunctional contact-enhancing agent at various interfaces to improve carrier mobility through the organic semiconductor layer, to improve carrier injection, and to enhance adhesion via a bifunctional mechanism. The contact-enhancing agent can be situated between the gate electrode (2) and the dielectric layer (3) to form a chemical or physical bond between the gate electrode and the dielectric layer. It can also be situated between the dielectric layer and the organic semiconducting layer (4), or between the source and drain electrodes (5, 6) and the organic semiconducting layer.

Abstract: Integrated circuit capacitors in which the capacitor dielectric is a thin film of BST having a grain size smaller than 200 nanometers formed above a silicon germanium substrate. Typical grain sizes are 40 nm and less. The BST is formed by deposition of a liquid precursor by a spin-on process. The original liquid precursor includes an alkoxycarboxylate dissolved in 2-methoxyethanol and a xylene exchange is performed just prior to spinning. The precursor is dried in air at a temperature of about 400° C. and then furnace annealed in oxygen at a temperature of between 600° C. and 850° C.

Abstract: A hetero field effect transistor according to the present invention comprises an InP substrate, a channel layer provided on the InP substrate with a buffer layer disposed between the InP substrate and the channel layer, a spacer layer constituted by a semiconductor having a band gap larger than that of the channel layer formed to hetero-join to the channel layer, and a carrier supply layer formed to be adjacent to the spacer layer, wherein the channel layer comprises a predetermined semiconductor layer constituted by a compound semiconductor represented by a formula GaxIn1?xNyA1?y in which A is As or Sb, composition x satisfies 0?x?0.2, and composition y satisfies 0.03?y?0.10.

Abstract: The present invention provides a simple method for forming the poly-Si and single crystalline Si TFT, which includes forming a line peninsular layer extending from an a-Si island layer at the active region. Then, a laser annealing process is performed, so that the re-crystallization will occur starting from an end of the line peninsular layer and then form the silicon island layer, serving as the active region for the TFT.

Abstract: The invention relates to a Schottky diode in which p-doped regions (4, 5) are incorporated in the Schottky contact area. At least one (5) of these regions (4, 5) has a greater minimum extent, in order to initiate a starting current.

Abstract: A nitride semiconductor light-emitting device includes an emission layer (103) formed on a substrate (100), and the emission layer includes a quantum well layer of GaN1-x?y?zAsxPySbz (0<x+y+z?0.3) containing Al.

Abstract: The present invention includes a chemical monolayer construction that comprises: a substrate having a contact surface, and a monolayer of a plurality of substantially parallel molecular units attached to the contact surface of the substrate. The molecular units are strongly coupled electronically to the substrate. The contact surface of the substrate has a roughness value less than or equal to the average length of the molecular units. The molecular units comprise a chemical structure that is capable of being changed from a relatively non-conductive state to a relatively conductive state by the application of a stimulus. The present invention also includes electronic circuit components and devices including chemical monolayer constructions.

Abstract: A method for fabricating p-type, i-type, and n-type III-V compound materials using HVPE techniques is provided. If desired, these materials can be grown directly onto the surface of a substrate without the inclusion of a low temperature buffer layer. By growing multiple layers of differing conductivity, a variety of different device structures can be fabricated including simple p-n homojunction and heterojunction structures as well as more complex structures in which the p-n junction, either homojunction or heterojunction, is interposed between a pair of wide band gap material layers. The provided method can also be used to fabricate a device in which a non-continuous quantum dot layer is grown within the p-n junction. The quantum dot layer is comprised of a plurality of quantum dot regions, each of which is typically between approximately 20 and 30 Angstroms per axis. The quantum dot layer is preferably comprised of AlxByInzGa1-x-y-zN, InGaN1-a-bPaAsb, or AlxByInzGa1-x-y-zN1-a-bPaAsb.

Abstract: A CMOS image sensor and a method for manufacturing the same, capable of preventing an interface between an active region and a field region in the CMOS image sensor from being damaged by ion implantation. The method comprises the steps of depositing a sacrificial oxide layer and a hard mask layer on a semiconductor substrate; etching the sacrificial oxide layer and the hard mask layer to form a mask pattern; etching the substrate to a predetermined depth to form a trench; depositing an isolating material in the trench and planarizing it until substantially coplanar with the hard mask layer; removing the hard mask layer to leave a protrusion in the isolating layer; depositing an insulating layer on the substrate and isolating layer; and etching the insulating layer and the sacrificial oxide layer sufficiently to form a spacer mask and expose the surface of the substrate.