Abstract: An improved, surface-passivated and electrically isolated solid-state device (including integrated circuits) comprises a silicon wafer with a PN junction or other electronic rectifying barrier contained therein and thermally grown or ion-implanted oxide or nitride isolating grooves in-situ formed in the wafer to isolate it into a plurality of physically integral pockets for use as electrically separately operable components. The grooves have symmetrical, centrally rounded bottoms which are located within a few microns below the PN junction or rectifying barrier. Through the unique oxide/nitride forming conditions and through curvature, symmetry, and proximity effects, novel passivation and isolation results obtain.

Abstract: In an optical transmitter in which the amount of light of an LD is monitored by a monitor PD, and the power of the LD is kept constant by feedback, the present invention aims to provide an optical transmitter that is suitable for size and cost reductions while being able to input a greater amount of the LD light of to the monitor PD, and that is capable of performing higher-bit-rate transmission. The present invention is characterized in that a concave groove is formed in a substrate, and the monitor photodiode is mounted on a slanted face of the concave groove, and the light of the LD that is oppositely and horizontally disposed is received directly by the monitor the LD photodiode.

Abstract: A light-emitting device and a method for manufacturing the same are described, by forming a SiN/Al1-x-yInxGayN(0?x?1, 0?y?1, x+y?1) superlattice layer between a substrate and an undoped GaN as a buffer layer, so as to reduce dislocation density of the buffer layer. In the SiN/Al1-x-yInxGayN(0?x?1, 0?y?1, x+y?1) superlattice layer, Al1-x-yInxGayN(0?x?1, 0?y?1, x+y?1) can be n-type, p-type or undoped.

Abstract: Quantum nanowires are produced in a medium comprising ions, dopants and free electrons, wherein the free electrons are solvated by complexes of ions and dopants. Electrical conductivity of the quantum nanowires can be higher than for conventional metal conductors. Quantum nanowires can be prepared in linear or circular form, and can be used to manufacture electrical components including transistors, sensors, motors and other nanoscale passive or active devices. Nanoscale devices can be made in liquid, semisolid, or solid media. Methods are provided for the manufacture of quantum nanowires and devices made therefrom. The devices can be used in the manufacture of computers, electronic circuits, biological implants and other products.

Abstract: A white LED device includes a member, a plurality of LEDs, fixed on the member, the LEDS further comprising blue GaN LEDs, a reflector, in parabolic shape, to encase thed member and the plurality of LEDs, yellow phosphor, coated on the surface of the reflector facing the LEDs, and a supporting component, for connecting the member and the reflector in order to connect the LEDs, the member and the reflector together. The main feature of the present invention includes that the LEDs emit blue light when positively biased. The blue light triggers yellow phosphor to generate a yellow light, and the blue light mixed with the yellow light to become a white light. The white light is reflected by the reflector to project onto target objects.

Abstract: A light-emitting thyristor having an improved luminous efficiency is provided. According to the light-emitting thyristor, a p-type AlGaAs layer and an n-type AlGaAs layer are alternately stacked to form a pnpn structure on a GaAs buffer layer formed on a GaAs substrate, and Al composition of the AlGaAs layer just above the GaAs buffer layer is increased in steps or continuously.

Abstract: An integrated circuit and fabrication method includes a memory cell for a dynamic random access memory (DRAM). Vertically oriented access transistors are formed on semiconductor pillars on buried bit lines. Buried first and second gates are provided for each access transistor on opposing sides of the pillars. Buried word lines extend in trenches orthogonal to the bit lines. The buried word lines interconnect ones of the first and second gates. In one embodiment, unitary gates are interposed and shared between adjacent pillars for gating the transistors therein. In another embodiment, separate split gates are interposed between and provided to the adjacent pillars for separately gating the transistors therein. In one embodiment, the memory cell has a surface area that is approximately 4 F2, where F is a minimum feature size. Bulk-semiconductor and semiconductor-on-insulator (SOI) embodiments are provided.

Abstract: By exploiting an intense correlation exhibited between the distribution of lattice distortions in a wafer and the distribution of the threshold voltages of field effect transistors, the distribution of the lattice distortions in the wafer is reduced, thereby to mitigate the distribution of the characteristics of the semiconductor elements in the wafer. The difference between the maximum value and minimum value of the lattice distortions of a III-V single crystal at a normal temperature is set to at most 4×10−5, and the density of Si atoms contained in the III-V single crystal is set to at most 1×1016 cm−3, whereby the characteristics of semiconductor elements whose parent material is the III-V single crystal can be made uniform.

Abstract: An organic field-effect transistor comprises source and drain electrodes formed separately from each other on a substrate, wherein the substrate comprises at least an organic semiconductor layer constituting a channel between the source and drain electrodes, an insulation layer underlying the organic semiconductor layer, and a gate electrode formed on the opposite side of the isolation layer. The organic semiconductor layer comprises hole and electron transporters, wherein the electron transporters comprise (6,6)-phenyl C61-butyric acid methyl ester (PCBM), and wherein the hole transporters comprise poly(2-methoxy-5-(3′,7′-dimethyloctyloxy)-1,4-phenylene-vinylene)(OC1C10-PPV) and/or poly(3-hexylthiophene) (P3HT).

Abstract: A semiconductor device is provided in which: a parasitic capacitance between a drain and a supporting substrate is reduced; and a high electric field generated in the vicinity of the drain is relaxed and which has a high withstand voltage. A MOS transistor according to the present invention includes: a supporting substrate region in an SOT substrate; a buried insulating film formed on the supporting substrate region; a channel region formed on the buried insulating film; and first and second offset regions that are formed on the buried insulating film so as to be adjacent to the channel region on both sides thereof, and further includes an impurity diffusion region formed in a portion positioned below the second offset region in the supporting substrate region.

Abstract: A semiconductor device includes: a crystalline substrate including a primary surface and a crystal plane provided within the primary surface so as to have a surface orientation different from a surface orientation of the primary surface; a semiconductor layered structure grown over the crystalline substrate; and an active region provided at a portion in the semiconductor layer structure above the crystal plane.

Abstract: A surge protection device includes a gate electrode embedded in an insulator, a source electrode and a drain electrode on the insulator. The source and drain electrodes respectively form first and second capacitances with the gate electrode. A semiconductor island is provided on the insulator to form a channel between the source and drain electrodes and a third capacitance with the gate electrode. The third capacitance is smaller than either of the first and second capacitances. The source and drain electrodes are adapted for connection to external circuitry for establishing a low-impedance path when the external circuitry is subjected to a surge potential.

Abstract: An SOI transistor element and a method of fabricating the same is disclosed, wherein a high concentration of stationary point defects is created by including a region within the active transistor area that has a slight lattice mismatch. In one particular embodiment, a silicon germanium layer is provided in the active area having a high concentration of point defects due to relaxing the strain of the silicon germanium layer upon heat treating the transistor element. Due to the point defects, the recombination rate is significantly increased, thereby reducing the number of charged carriers stored in the active area.

Abstract: An organic electroluminescent device including at least one organic thin film layer interposed between an anode and a cathode, the at least one organic thin film layer including a luminescent zone having at least one luminescent layer, wherein the organic thin film layer contains a compound represented by one of the following general formulae [I], [II], and [III]: A1-X1-(A2)a  [I] XN-(Y)n  [II] Y1-Y2  [III] Since the light emission from layers other than the luminescent zone (luminescent layer) is significantly decreased in this organic EL device, the color purity of the light emitted by the device is improved, thus providing a highly efficient, high luminance organic electroluminescent device.

Abstract: The invention relates to a light source comprising a light-emitting element, which emits light in a first spectral region, and comprising a luminophore, which comes from the group of alkaline-earth orthosilicates and which absorbs a portion of the light emitted by the light source and emits light in another spectral region. According to the invention, the luminophore is an alkaline-earth orthosilicate, which is activated with bivalent europium and whose composition consists of: (2-x-y)SrOx(Ba, Ca)O(1-a-b-c-d)SiO2aP2O5bAl2O3cB2O3dGeO2:yEu2+ and/or (2-x-y)BaOx((Sr, Ca)O(1-a-b-c-d)SiO2aP2O5bAl2O3cB2O3dGeO2:yEu2+. The desired color (color temperature) can be easily adjusted by using a luminophore of the aforementioned type.

Abstract: An organic light-emitting device including a transparent substrate, a first electrode layer, a second electrode layer, a hole-transporting layer, and a electron-transporting layer sandwiched between the first and second electrode layers, wherein the hole-transporting layer consists of organic multiple-quantum-well structure. The multiple-quantum-well structure has a period number of alternating layers formed of a layer of organic material A with wide energy gap and a layer of organic material B with narrow energy gap. Organic material A and organic material B are selected such that the highest occupied molecular orbital (HOMO) levels of organic material A are lower than those of organic material B and the lowest unoccupied molecular orbital (LUMO) levels of organic material A are higher than those of organic material B.

Abstract: A control system for an array of qubits is disclosed. The control system according to the present invention provides currents and voltages to qubits in the array of qubits in order to perform functions on the qubit. The functions that the control system can perform include read out, initialization, and entanglement. The state of a qubit can be determined by grounding the qubit, applying a current across the qubit, measuring the resulting potential drop across the qubit, and interpreting the potential drop as a state of the qubit. A qubit can be initialized by grounding the qubit and applying a current across the qubit in a selected direction for a time sufficient that the quantum state of the qubit can relax into the selected state. In some embodiments, the qubit can be initialized by grounding the qubit and applying a current across the qubit in a selected direction and then ramping the current to zero in order that the state of the qubit relaxes into the selected state.

Abstract: The present invention is a semiconductor structure for light emitting devices that can emit in the red to ultraviolet portion of the electromagnetic spectrum. The semiconductor structure includes a Group III nitride active layer positioned between a first n-type Group III nitride cladding layer and a second n-type Group III nitride cladding layer, the respective bandgaps of the first and second n-type cladding layers being greater than the bandgap of the active layer. The semiconductor structure further includes a p-type Group III nitride layer, which is positioned in the semiconductor structure such that the second n-type cladding layer is between the p-type layer and the active layer.

Abstract: The present invention discloses a light-emitting diode with enhanced light-emitting efficiency, in which the active current is prevented from flowing in the region under the top electrode so that the light-emitting efficiency as well as the brightness can be improved.

Abstract: A multi-layer Auger suppressed diode having at least two exclusion interfaces and at least two extraction interfaces. A specific embodiment has two composite contacts, each consisting of a heavily doped layer (3, 4) and a buffer layer (8, 9) of lower doped, high bandgap material sandwiched between the heavily doped layer and the active region (2) of the device.