Abstract: Composite material (10) comprises a substrate (1) and a chemically, mechanically, physically, catalytically and/or optically functional titanium oxide layer (2), applied on at least one side thereof. A titanium oxide layer (2) is deposited on the substrate (1) as a base layer (3), made from TiOx with an oxygen content of 0.7?x<2, or made from TiOx(OH)y with an oxygen content of 0.5?x<2 and a hydroxide content of 0?y<0.7 and an upper layer (4) of amorphous and/or crystalline TiO2 applied to said base layer (3). In a first method variation, firstly a base layer (3) of TiOx with an oxygen content of 0.7?×<2 is reactively or non-reactively deposited, then, through an increase in the oxygen content, the process pressure, the capacity and/or the substrate temperature, an upper layer (4) of amorphous and/or crystalline TiO2 is deposited. In a second method variation, firstly a base layer (3) of TiOx with an oxygen content of 0.

Abstract: A semiconductor device includes an active region, an alternating conductivity type layer, and an insulation region surrounding the alternating conductivity type layer provided in a periphery section as a voltage withstanding section. The insulation region is made of an insulator with the critical electric field strength higher than that of the semiconductor and reaches an n+-drain layer on the bottom surface side of the device from a surface on the side on which a surface structure section is formed. In the alternating conductivity type layer, the width of the p-type partition region adjacent to the insulation region is made narrower than the width of the p-type partition region not adjacent to the insulation region to ensure a balanced state of charges at the end of the drift section made up of the alternating conductivity type layer. A high breakdown voltage is ensured with the length of the periphery section shortened.

Abstract: There is provided a crystalline TFT in which reliability comparable to or superior to a MOS transistor can be obtained and excellent characteristics can be obtained in both an on state and an off state. A gate electrode of the crystalline TFT is formed of a laminate structure of a first gate electrode made of a semiconductor material and a second gate electrode made of a metal material. An n-channel TFT includes an LDD region, and a region overlapping with the gate electrode and a region not overlapping with the gate electrode are provided, so that a high electric field in the vicinity of a drain is relieved, and at the same time, an increase of an off current is prevented.

Abstract: A ground-enhanced semiconductor package and a lead frame used in the package are provided. The semiconductor package includes a lead frame having a die pad, a plurality of tie bars connected with and supporting the die pad, a plurality of leads surrounding the die pad, and a ground structure, wherein the ground structure comprises at least one of first ground portions connected to the tie bars, and/or at least one of second ground portions connected to the die pad, and wherein the first ground portions are separate from each other, and the second ground portions are separate from each other; at least one chip mounted on the die pad and electrically connected to the leads and the ground structure; and an encapsulation body for encapsulating the chip and the lead frame. The separately-arranged ground portions allow thermal stresses to be released from the ground structure without rendering deformation issues.

Abstract: A method and apparatus for depositing self-aligned base contacts where over-etching the emitter sidewall to undercut the emitter contact is not needed. A semiconductor structure has a T-shaped emitter contact that comprises a T-top and T-foot. The T-top acts as a mask for depositing the base contacts. In forming the T-top, its dimensions may be varied, thereby allowing the spacing between the base contacts and emitter to be adjusted.

Abstract: Apparatus and methods are provided for integrating microchannel cooling modules within high-density electronic modules (e.g., chip packages, system-on-a-package modules, etc.,) comprising multiple high-performance IC chips. Electronic modules are designed such that high-performance (high power) IC chips are disposed in close proximity to the integrated cooling module (or cooling plate) for effective heat extraction. Moreover, electronic modules which comprise large surface area silicon carriers with multiple chips face mounted thereon are designed such that integrated silicon cooling modules are rigidly bonded to the back surfaces of such chips to increase the structural integrity of the silicon carriers.

Abstract: A high fill-factor photosensor array is formed comprising a P-layer, an I-layer, one or more semiconductor structures adjacent to the I-layer and each coupled to a N-layer, an electrically conductive electrode formed on top of the P-layer, and an additional semiconductor structure, adjacent to the N-layer and which is electrically connected to a voltage bias source. The bias voltage applied to the additional semiconductor structure charges the additional semiconductor structure, thereby creating a tunneling effect between the N-layer and the P-layer, wherein electrons leave the N-layer and reach the P-layer and the electrically conductive layer. The electrons then migrate and distribute uniformly throughout the electrically conductive layer, which ensures a uniform bias voltage across to the entire photosensor array. The biasing scheme in this invention allows to achieve mass production of photosensors without the use of wire bonding.

Abstract: A transistor and method of formation thereof includes source and drain extension regions in which the diffusion of dopants into the channel region is mitigated or eliminated. This is accomplished, in part, by elevating the source and drain extension regions into the epitaxial layer formed on the underlying substrate. In doing so, the effective channel length is increased, while limiting dopant diffusion into the channel region. In this manner, performance characteristics of the transistor can be accurately determined by controlling the respective geometries (i.e. depths and widths) of the source/drain extension regions, the source/drain regions, the channel width and an optional trench formed in the underlying substrate. In the various embodiments, the source/drain regions and the source/drain extension regions may extend partially, or fully, through the epitaxial layer, or even into the underlying semiconductor substrate.

Abstract: The present invention provides a switching element in which an organic bistable material is disposed between two electrodes, this element having a high ratio of ON current to OFF current, a high threshold voltage, and a small spread. A switching element in which an organic bistable material layer comprising an organic bistable material having two stable values of resistance with respect to the applied voltage is disposed between at least two electrodes, wherein an organic material layer is provided between the organic bistable material layer and at least one of the electrodes. Electrically conductive fine particles are preferably dispersed in the organic materials layer.

Abstract: An LED lamp according to the present invention includes: a substrate 10 having a principal surface 10a; at least one LED 12, which is supported on the principal surface 10a of the substrate 10; a reflector 16, which has an opening that defines a reflective surface 14 surrounding the side surface of the LED 12 and which is supported on the principal surface 10a of the substrate 10; and an encapsulating resin layer 18, which covers the LED 12 and the reflector 16 together. When a portion of the encapsulating resin layer 18 that covers the side surfaces 16w of the reflector 16 has a thickness Dw and another portion of the encapsulating resin layer 18 that covers the upper surface 16h of the reflector 16 has a thickness Dh, the LED lamp has a Dh/Dw ratio of 1.2 to 1.8.

Abstract: A device is provided which includes a single-crystal semiconductor region disposed in a substrate. The single-crystal region includes a first semiconductor material and a diode disposed in the single-crystal region. The diode includes an anode region including a first alloy region, being an alloy of the first semiconductor material with a second semiconductor material, and a second region which consists essentially of the first semiconductor material, the diode further including a cathode region.

Abstract: This invention is characterized in that, a gate electrode 27F formed on a P-type well 3 via a gate oxide film 9, a high-concentration N-type source layer and a high-concentration N-type drain layer 15 respectively formed apart from the gate electrode and a low-concentration N-type source layer and a low-concentration N-type drain layer respectively formed so that they respectively surround the N-type source layer and the N-type drain layer 10 and respectively parted by a P-type body layer formed under the gate electrode 27F are provided.

Abstract: A method of manufacturing an integrated circuit provides a substrate having a semiconductor device, and includes forming an intermetal dielectric layer over the substrate and the semiconductor device. A metal wire is formed above the semiconductor device and in contact therewith and a passivation layer is formed over the intermetal dielectric layer. A bond pad is formed connected to the metal wire. A protective moat, with sidewall passivation layer, is formed through the passivation layer and the intermetal dielectric layer, and is located between the metal wire and an outside edge of the integrated circuit.

Abstract: A display device of the present invention comprises: a source line; a pixel electrode; a first TFT for switching an electrical connection between the source line and the pixel electrode; and a second TFT as a spare. The second TFT includes a semiconductor film and a gate electrode. The semiconductor film includes a source electrode and a drain electrode. The gate electrode is provided on the semiconductor film with a gate insulation film interposed therebetween. The display device includes an interlayer insulation film between the source line and the semiconductor film of the second TFT. The interlayer insulation film is thicker than the gate insulation film. When the first TFT is unusable, a contact hole is formed in the interlayer insulation film such that the source line is electrically connected to the source electrode, whereby the electrical connection between the source line and the pixel electrode is rendered switchable by the second TFT.

Abstract: A NTCDA single crystal is used as a photoelectric current multiplier layer, and Au thin films are formed as electrodes on the opposite surfaces of the multiplier layer by a vapor deposition method to form a sandwich type cell. When a voltage is applied to the NTCDA single crystal by the electrodes from a dc power source and a monochromatic light is applied, a multiplied photoelectric current flows between the electrodes. A rise of this element at light-on is considerably faster than when a vapor-deposited layer is used as a photoelectric current multiplier layer to permit a faster response.

Abstract: A semiconductor device includes: an insulating underlying layer of which surface portion has a concave portion; a lower electrode formed on the underlying layer along the inner face of the concave portion; a capacitor insulating film formed on the lower electrode and made of a high-dielectric or a ferroelectric subjected to thermal treatment for crystallization; and an upper electrode formed on the capacitor insulating film. The lower electrode and the upper electrode are made of a material that generates tensile stress in the thermal treatment for the capacitor insulating film, and the upper end part of the side wall and the corner part at the bottom face of the concave portion of the underlying layer are rounded.

Abstract: An InGaN active layer is formed on a sapphire substrate. A p-side electrode is formed on the InGaN active layer to supply an electric current to this InGaN active layer. The p-side electrode includes {circle around (1)} an Ni layer for forming an ohmic contact with a p-GaN layer, {circle around (2)} an Mo layer having a barrier function of preventing diffusion of impurities, {circle around (3)} an Al layer as a high-reflection electrode, {circle around (4)} a Ti layer having a barrier function, and {circle around (5)} an Au layer for improving the contact with a submount on a lead frame. The p-side electrode having this five-layered structure realizes an ohmic contact and high reflectance at the same time.

Abstract: An example memory includes an address control portion, a protection film, a property deterioration material layer, data storage areas, and bonding pads. The protection film protects an organic semiconductor layer of a semiconductor circuit and prevents intrusion of moisture or chemical molecules in the air, light, or the like, into the organic semiconductor layer. Deterioration of the organic semiconductor layer is started by breaking the protection film and using a specified means, thus starting operation of the lifetime period. The property deterioration material layer contains a material for deteriorating the property of the organic semiconductor and deterioration of the organic semiconductor layer is started, for example, by diffusing the material into the organic semiconductor layer.

Abstract: A chip is provided which includes an active semiconductor region and a field effect transistor (“FET”) having a channel region, a source region and a drain region all disposed within the active semiconductor region. The FET has a longitudinal direction in a direction of a length of the channel region, and a transverse direction in a direction of a width of the channel region. A first dielectric stressor element having a horizontally extending upper surface extends below a portion of the active semiconductor region, such as a northwest portion of the active semiconductor region. A second dielectric stressor element having a horizontally extending upper surface extends below a second portion of the active semiconductor region, such as a southeast portion of the active semiconductor region. Each of the first and second dielectric stressor elements shares an edge with the active semiconductor region, the edges extending in directions away from the upper surface.

Abstract: A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate (1) in a low-voltage NMOS region (LNR) thereby to form extension layers (61). Then, a silicon oxide film (OX2) is formed to cover the whole surface of the silicon substrate (1). The silicon oxide film (OX2) on the side surfaces of gate electrodes (51–54) is used as an offset sidewall. Then, boron is ion implanted to a relatively low concentration in the surface of the silicon substrate (1) in a low-voltage PMOS region (LPR) thereby to form P-type impurity layers (621) later to be extension layers (62).