Abstract: It is suggested for a metal-semiconductor diode that the depletion zone layer be grown epitaxially from deformed In.sub.x Ga.sub.1-x As with an indium content x increasing in the direction of the metal contact and/or that a diode area be delimited by surrounding insulation regions in a planar design consisting of a flat layer sequence and that the metal contact be provided on the surface of the layer sequence. Corresponding advantageous manufacturing processes are described.

Abstract: A Coulomb-blockade element includes a silicon layer formed on a substrate through an insulating film. The silicon layer includes a narrow wire portion and first and second electrode portions. The narrow wire portion serves as a conductive island for confining a charge. The first and second electrode portions are formed to be connected to the two ends of the narrow wire portion and are wider than the narrow wire portion. Each of the first and second electrode portions has constrictions on at least one of the upper and lower surfaces thereof, which make a portion near the narrow wire portion thinner than the narrow wire portion.

Abstract: An integrated-circuit interconnect which can be formed at the wafer level is achieved by depositing an intentionally stressed contact layer over a release layer which is subsequently removed. The removal of the release layer permits a portion of the contact layer to curve away from the surface of an integrated chip. The result is a spring contact having a base portion joined to a member of the chip and a spring portion which is available for joining of other metal members, e.g., on a substrate or another chip. The resilience of the spring portion can also be used to position and align integrated circuit elements.

Abstract: This is a device package comprising: a leadframe comprising a plurality of leads for effecting circuit connections to the device; and a metal ground piece connected to the leadframe. Other devices and methods are also disclosed.

Abstract: A ROM semiconductor device and a method of manufacturing that device on a semiconductor substrate comprises the steps of forming a blanket word line layer over the device with a reverse word line mask over the word line layer, the word line mask comprising a parallel array of mask strips, forming a ROM code mask over the reverse word line mask, the ROM code mask having a ROM code opening centered between a pair of the mask strips. A code implant dopant is ion implanted through the ROM code opening down into a doped region in the substrate below the ROM code opening. The ROM code mask is removed. A word line mask is formed comprising complementary mask strips between the mask strips of the reverse word line mask followed by removal of the reverse word line mask, etching the word line layer to form a parallel array of word lines beneath the complementary mask strips, and forming a blanket layer of dielectric material over the device.

Abstract: A chip mounting plate construction of lead frames for semiconductor packages which provides a chip mounting plate having a greatly reduced area to obtain a small bonding area between the chip mounting plate and a semiconductor chip mounted on the chip mounting plate, thereby capable of minimizing thermal strain generated at the chip mounting plate due to a thermal expansion thereof. The chip mounting plate is constructed to have a smaller area than the semiconductor chip, to have a central opening, or to have recesses.

Abstract: A semiconductor device and process for making the same are disclosed which use porous dielectric materials to reduce capacitance between conductors, while allowing conventional photolithography and metal techniques and materials to be used in fabrication. In one structure, patterned conductors 18 are provided on an interlayer dielectric 10, with a substrate encapsulation layer 31 deposited conformally over this structure. A layer of porous dielectric material 22 (e.g. dried SiO.sub.2 gel) is then deposited to substantially fill the gaps between and also cover the conductors. A substantially solid cap layer 14 of a material such as SiO.sub.2 is then deposited, followed by a photolithography step to define via locations. Vias are etched through the cap layer, and then through the porous dielectric.

Abstract: A previously unknown phase of .alpha.-hexathienyl, designated .alpha.-6T/HT, exhibits diffraction peaks at 2.theta.=4.31.degree., 8.64.degree., 12.96.degree., 17.32.degree., 26.15.degree. and 29.08.degree. in a CuK.sub..alpha. powder X-ray diffraction pattern, and is expected to have properties (e.g., high hole mobility) that make the phase desirable for use in, e.g., thin film transistors. Substitution of thin films of .alpha.-6T/HT for prior art organic thin films in thin film transistors and other devices is contemplated.

Abstract: A method of producing a semiconductor device includes the steps of fitting a bottom part of a radiator block within a tapered hole which is provided at a bottom of a recess of a jig and positioning on the jig a lead frame having inner and outer leads and wherein the lead frame has an opening at a central part thereof, the opening being located above a top surface of the radiator block. The semiconductor chip is then mounted on the top surface part of the radiator block and bonded to the lead frame by plurality of wires.

Abstract: An integrated circuit device for acceleration detection (100) includes a thick substrate (1) and a semiconductor strain sensor (2) provided on the thick substrate (1) with conductive solder bump electrodes (8) interposed therebetween. The semiconductor strain sensor (2) has a mass holding part (2b), an acceleration sensing part (2a) provided with a piezoresistance layer, a base end part (2c) fixed on the solder bump electrode (8) and a balance keeping part (2d). Electric signals obtained from the semiconductor strain sensor (2) are connected to pattern wiring lines (7) which are provided on the thick substrate (1) by means of the solder bump electrode (8) interposed therebetween. A space (W) between the thick substrate (1) and the mass holding part (2b) depends upon the solder bump electrode (8).

Abstract: A semiconductor device is provided which comprises: a semiconductor chip having a semiconductor substrate, an insulation a film, a field oxide film and pads formed on a surface thereof; bumps respectively formed on the pads; inner leads bonded to the semiconductor chip with intervention of bumps; a metal interconnection formed in an indentation which is formed between the pads and an edge of the semiconductor chip by removing part of the insulation film and/or the field oxide film of the semiconductor chip; and a pair of dummy electrodes respectively formed between each of the pads and the metal interconnection and between the metal interconnection and the edge of the chip at a higher elevation than the metal interconnection and spaced apart a predetermined distance from the metal interconnection, the pair of dummy electrodes being provided for each of the inner leads, which is located thereabove.

Abstract: A microelectronic integrated circuit includes a semiconductor substrate, and a plurality of microelectronic devices formed on the substrate. Each device has a periphery defined by a hexagon, and includes an active area formed within the periphery. A first terminal and a second terminal are formed in the active area adjacent to edges of the hexagon that are separated by another edge. First to third gates are formed between the first and second terminals, and have gate terminals formed outside the active area adjacent to other edges of the hexagon. The power supply connections to the first and second terminals, the conductivity type (NMOS or PMOS), and the addition of a pull-up or a pull-down resistor is selected for each device to provide a desired AND, NAND, OR or NOR function. The devices are interconnected using three direction routing based on hexagonal geometry.

Abstract: A thin film transistor (TFT) having a reduced channel length and method of making same are disclosed for liquid crystal display (LCD) applications. The method of making the TFT includes the following process steps: (i) depositing and patterning the gate on a substrate; (ii) depositing and patterning an intrinsic a-Si layer, a n+ a-Si layer, and a source metal layer (e.g. Cr) over the gate; (iii) depositing and patterning an ITO layer to form a pixel electrode portion and a TFT source portion; (iv) etching the source metal layer so that it remains only under the ITO source portion so as to form the TFT source electrode; (v) depositing and patterning a metal (e.g. Mo) to form the drain of the TFT; and (vi) etching the n+ a-Si layer in the TFT channel area so that only the intrinsic semiconductor layer remains between the source and drain. The resulting TFT has a reduced channel length (e.g. less than about 4 .mu.m) less than the feature size of the lithography used so as to maximize I.sub.ON /C.sub.

Abstract: Solder interconnection encapsulant, encapsulated structure and method for its fabrication and use, whereby the gap created by solder connections between a carrier substrate and a semiconductor device is filled with a composition obtained from curing a preparation containing a cycloaliphatic polyepoxide and/or curable cyanate ester or prepolymer thereof; filler, e.g., an aluminum nitride or aluminum oxide filler, having a maximum particle size of 31 microns.

Abstract: A semiconductor integrated device having a non-volatile memory element or memory cell of a single-element type in a non-volatile memory circuit employing a field effect transistor which has, in addition to a floating gate electrode for storage of information and a controlling gate electrode, a source which includes a heavily doped region having a depth into the semiconductor substrate extending from the major surface thereof which is large. The single-element type field effect transistor, furthermore, has a drain which includes a lightly doped region which has a depth extending into the semiconductor substrate from the major surface thereof which is small.

Abstract: A semiconductor photo detector has its construction such that on a substrate made of InP are formed light absorption layer having a supperlattice structure made of n- type InGaAsP and InAsP, an intermediate layer made of n- type InGaAs, a multiplication layer made of n- type InP and a layer made of p- type layer. The light having a wavelength 1.65 .mu.m being made incident into the detector from the p- type InP layer is absorbed in the superlattice structure light absorption layer of n- type InGaAs/InAsP and changed into carriers, which flowed out an external circuit. Since the superlattice of InGaAs and InAsP makes a lattice matching to InP, it may be possible to prevent that a dark current is generated by a lattice mismatching. The carriers generated by the absorbed light in the light absorption layer pass from the p type side electrode 11 into an external circuit via the n type InGaAsP intermediate layer 4, n+ type InP multiplication layer 5 and p+ type InP layer 8.

Abstract: An impurity diffusion surface layer is formed in a surface of a silicon substrate, and an aluminum electrode is arranged in direct contact with the impurity diffusion layer. The surface layer contains Ge as an impurity serving to change the lattice constant in a concentration of at least 1.times.10.sup.21 cm.sup.-1 under a thermal non-equilibrium state. The lattice constant of the surface layer is set higher than that of silicon containing the same concentration of germanium under a thermal equilibrium state. As a result, it is possible to decrease the Schittky barrier height at the contact between the surface layer and the electrode. The surface layer also contains an electrically active boron as an impurity serving to impart carriers in a concentration higher than the critical concentration of solid solution in silicon under a thermal equilibrium state. The presence of Ge permits the carrier mobility within the surface layer higher than that within silicon.

Abstract: Integrated circuits running with high frequencies are a potential source for RFI (Radio Frequency Interference). To reduce RFI, on-chip dedoupling capacitors are included in the design. To gain maximum advantage of these decoupling capacitors, they should be placed close to drivers and flip-flops. In a standard cell design approach for fabrication of the ICs, capacitors are embedded below the power supply lines. These capacitors are put in special cells, called cap-cells, which are placed by the place and route software on either side of each row of standard cells. Thin oxide capacitors are preferred because they offer the largest capacitance per area. In addition, first and second metal above the capacitor are increased to form thick oxide capacitors that give additional capacitance.

Abstract: Bonding pads are formed on a main surface of a semiconductor chip. An insulating layer having openings located on the bonding pads is formed on the main surface of the semiconductor chip. Base metal layers are formed on the bonding pads. A buffer coat film having a portion laid on a periphery of the base metal layer is formed on the insulating layer. Connection layers are formed on the base metal layers. First conductors are formed on the connection layers. A seal resin exposing only top surfaces of the first conductors is formed. Lumpish second conductors are formed on the top surfaces of the first conductor. Thereby, a resin seal semiconductor package can be made compact and it has improved electrical characteristics and high reliability.

Abstract: A semiconductor integrated circuit device includes in a substrate a P-type well region containing a memory array section in which dynamic memory cells are arranged in a matrix. The P-type well region is fed with a back bias voltage whose absolute value is reduced so as to be the most suitable for the refresh characteristics. Also included is a P-well region wherein there are formed N-channel MOSFETs of a peripheral circuit this P-well region is fed with a back bias voltage whose absolute value is smaller than that of the potential fed to the P-type well of the memory array section, considering the high-speed operation. A P-type well section, wherein there is formed are N-channel MOSFETs of an input circuit or an output circuit connected with external terminals, is fed with a back bias voltage whose absolute value is made large considering an undershoot voltage. The P-type well region provided with the memory array section is fed with a requisite minimum back bias voltage.