Abstract: In a semiconductor device, a layer of nitrogen doped polysilicon is applied to a gate oxide in turn provided on a semiconductor body, and then a silicide film is applied to the polysilicon layer. The nitrogen in the polysilicon layer inhibits growth of native oxide on the polysilicon layer prior to the application of silicide, and at subsequent high temperature processing steps, so that the problem of the silicide layer lifting from the polysilicon layer due to this native oxide growth is avoided during subsequent high temperature processing of the device.

Abstract: A power semiconductor device having internal circuits characterized by an electrical breakdown during one mode of operation is implemented with a protective circuit. The electrical breakdown is controllably induced to occur at the protective circuit thereby diverting any breakdown in the active circuits. In the preferred embodiment, the power device is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) in which the protective circuit is deposited as an annular diffusion ring having a shallow portion and a deep portion. The deep portion is higher in doping concentration than the shallow portion and includes a radius of curvature larger than the shallow portion. The radius of curvature of the deep portion can be adjusted to induce breakdown at or above the rated value of the MOSFET. The predetermined doping concentration of the deep portion can abort the breakdown prematurely to occur at the deep region instead of at the active circuits.

Abstract: An optoelectronic semiconductor device is provided in which carrier transport towards the active region thereof is enhanced by the formation of a miniband within a superlattice region of the device having a repeating pattern of first and second semiconductor regions. The minimum energy level of the miniband is equal to or greater than the energy level of a guiding region between the active region and the superlattice region.

Abstract: A bipolar transistor and a process for manufacturing thereof is disclosed. The bipolar transistor has a self-aligned base electrode in which first and second pillars are formed within first and second trenches which act as an activated region and a collector region, respectively; a conductive impurities layer of high density formed at a bottom side of the first and second trenches and at a lower portion of an isolation wall between the first and second trenches; and a sequentially formed base and emitter layer. After connection to the base layer, a base contact electrode is formed within the first trench, and a collector contact electrode is formed by implanting second conductive impurities in the second pillar.

Abstract: In a multichip module structure comprising a silicon, alumina or sapphire substrate carrying a plurality of layers of metallisation separated by polymer dielectric layers, with one or more inductors formed in the uppermost metallisation layer, a ferrite core for one of those inductors is located over the inductor and secured in position by flip chip solder bonding.

Abstract: A semiconductor substrate 4 consisting of an n.sup.+ -type substrate 1, an n.sup.- -type silicon carbide semiconductor layer 2 and a p-type silicon carbide semiconductor layer 3, made of hexagonal crystal-based single crystal silicon carbide with the main surface having a planar orientation approximately in the (0001) carbon face. An n.sup.+ -type source region 5 is formed in the surface layer of the semiconductor layer 3, and a trench 7 runs from the main surface through the region 5 and the semiconductor layer 3 reaching to the semiconductor layer 2, and extending approximately in the ?1120! direction.

Abstract: A bonded wafer with a bond junction having low resistivity due to the low level of oxides at the bond junction. A plasma that removes native oxide layers from wafers is exposed to the wafers. The plasma forms a hydrophobic polymer seal on the wafers, inhibiting subsequent native oxide growth upon exposure to air. The polymer seal on the wafers to be bonded are pressed together and the wafers are annealed to form the bonded wafer in a non-oxidizing ambient. The bond junction formed is primarily silicon to silicon and silicon to carbon bonds.

Abstract: A hot carrier transistor can be formed with semiconductor thin-film technology, for example hydrogenated amorphous silicon (a-Si:H) technology as used for large-area electronics devices. The emitter and collector regions (2 and 3) comprise hydrogenated amorphous semiconductor material (a-Si:H) adjoining an intermediate semiconductor-rich amorphous metal-semiconductor alloy layer (a-Si.sub.1-x M.sub.x :H) which provides the base region 1. The amorphous nature of the alloy layer (1) and its low percentage of metal M, e.g 5%, presents a range of quantum mechanical environments for the hot carriers (21) through the base region (1) with spatial variations of wavelength and effective mass (m*.sub.1, m*.sub.2). The current transport through this base region (1) will therefore be spatially self-selective in that the carriers (21) will tend to pass through those areas where there is a resonance between the wave function, the barrier heights (h1,h2) and the base width (x1,x2).

Abstract: Integrated circuit SRAM cells include a semiconductor substrate having a field region and first, second, third and fourth active regions therein. The first and second active regions each include a horizontal leg and a vertical leg and are mirror images of each other about a vertical axis. The third and fourth active regions each also include a horizontal leg and a vertical leg and are mirror images of each other about a vertical axis. The integrated circuit SRAM cells also include first and second vertically extending gate conductive layers on the semiconductor substrate. The first vertically extending conductive layer extends vertically over the first active region horizontal leg and extends vertically over the third active region horizontal leg. The second vertically extending conductive layer extends vertically over the second active region horizontal leg and extends vertically over the fourth active region horizontal leg.

Abstract: The present invention provides a superconducting switch which has a substrate base and a control line patterned thereon. A buffer layer is deposited on top of these and then a superconducting material is deposited and then patterned wherein the superconducting material forms a strip having multiple intersections with the control line. At each intersection between the control line and the superconducting strip is formed a superconducting gate due to the double step edge junction. The control line underneath provides (1) a means for constructing step edge weak link junctions; (2) a means for heating the weak link junctions; and (3) generating an electromagnetic field near the weak link junctions. In combination, a very small magnetic field can be used to decrease the critical current to a very low level.

Abstract: The present invention provides an AlGaInP light-emitting device with a longer life and higher reliability. The AlGaInP light-emitting device comprises an n-type (Al.sub.0.7 Ga.sub.0.3).sub.0.51 In.sub.0.49 P cladding layer (about 1 .mu.m in thickness), an (Al.sub.0.15 Ga.sub.0.85).sub.0.51 In.sub.0.49 P active layer (about 0.6 .mu.m in thickness), a p-type (Al.sub.0.7 Ga.sub.0.3).sub.0.51 In.sub.0.49 P cladding layer (about 1 .mu.m in thickness), and a p-type current-spreading layer composed of either a p-type Al.sub.0.7 Ga.sub.0.3 As layer (about 3 .mu.m in thickness) or a p-type Al.sub.0.7 Ga.sub.0.3 As.sub.0.97 P.sub.0.03 layer (about 3 .mu.m in thickness) and a p-type GaAs.sub.0.5 P.sub.0.5 layer (about 7 .mu.m in thickness), in sequence formed on an n-type GaAs substrate, and further an upper surface electrode mounted on the p-type GaAs.sub.0.5 P.sub.0.5 layer and a lower surface electrode mounted on the lower surface of the n-type GaAs substrate.

Abstract: Organic light emitting diodes having a transparent cathode structure is disclosed. The structure consists of a low work function metal in direct contact with the electron transport layer of the OLED covered by a layer of a wide bandgap semiconductor. Calcium is the preferred metal because of its relatively high optical transmissivity for a metal and because of its proven ability to form a good electron injecting contact to organic materials. ZnSe, ZnS or an alloy of these materials are the preferred semiconductors because of their good conductivity parallel to the direction of light emission, their ability to protect the underlying low work function metal and organic films and their transparency to the emitted light. Arrays of these diodes, appropriately wired, can be used to make a self-emissive display. When fabricated on a transparent substrate, such a display is at least partially transparent making it useful for heads-up display applications in airplanes and automobiles.

Abstract: An IC voltage clamp and a process for forming the voltage clamp. The voltage clamp includes an MGFO device having an n-type source region, an n-type drain region, and a p-type field implant diffusion between the source and drain regions. The voltage clamp further employs a parasitic NPN device having a collector region coincident with the MGFO drain region, an emitter region coincident with the MGFO source region, and a base region formed by the substrate. A metal gate electrode overlies and is insulated from the field implant diffusion, but electrically connects the source and emitter regions to ground. An input electrode contacts the drain region so as to electrically connect the drain and collector regions to the input voltage of an integrated circuit. The field implant diffusion and drain/collector regions are formed by overlapping their masks, such that a lower breakdown voltage is achieved between the NPN collector and the substrate and field implant diffusion (the NPN base).

Abstract: A trench isolation structure for a semiconductor is provided including an isolation ring and an isolation path. The isolation ring surrounds active semiconductor areas and is bordered on the outside by inactive semiconductor area. The isolation path extends from the isolation ring through the inactive semiconductor area. A first level conductor on the isolation path electrically connects or capacitively couples a device in the active semiconductor area to a location on the substrate outside the isolation ring. The isolation path has a configuration derived from the layout of the conductor.

Abstract: A semiconductor device (10) is formed in a semiconductor substrate (11) that acts as a collector region. A base region (12) is formed in the semiconductor substrate (11) and an emitter region (52) is formed such that it contacts at least a portion of the base region (12). A conductive layer (28) is used to provide electrical connection to the emitter region (52). The portion of the conductive layer (28) above the emitter region (52) is counter-doped to address the problems of an interfacial oxide layer (27) that exists between the emitter region (52) and the conductive layer (28).

Abstract: The single electron tunnel device of this invention includes: a multiple tunnel junction layer including multiple tunnel junctions; and first and second electrodes for applying a voltage to the multiple tunnel junction layer, wherein the multiple tunnel junction layer includes an electrically insulating thin film and metal particles and/or semiconductor particles dispersed in the electrically insulating thin film.

Abstract: An improved multichip semiconductor module compatible with existing SIMM memory sockets comprising a molded module frame and a composite semiconductor substrate subassembly received in a cavity in said frame. The composite semiconductor substrate subassembly or subassembly(s) comprises a plurality of semiconductor devices which are connected to electrical contacts on an edge of the molded frame by a variety of configurations described herein. In one embodiment of the invention, the subassembly(s) includes a composite substrate which comprises a thin metal cover plate and thin laminate circuit which is bonded to the metal cover plate by a film adhesive. The composite substrate provides a mounting surface for the placement of semiconductor devices and their associated passive components.

Abstract: A semiconductor device has a carrier, at least one semiconductor component provided on this carrier, and a multilayer metallization between the semiconductor component and the carrier. A first metal layer of aluminium, gold, or a gold alloy is provided on the surface of the semiconductor component, a second metal layer of titanium is provided on the first metal layer, a third metal layer of nickel is provided on the second metal layer, and a fourth metal layer of a binary or ternary gold-germanium alloy is provided on the third metal layer. The device has a low-ohmic contact resistance and extremely long useful life under temperature loads.

Abstract: Regions 106 which can be regarded as being monocrystalline are formed locally by irradiating with laser light, and at least the channel-forming region 112 is constructed using these regions. With thin-film transistors which have such a construction it is possible to obtain characteristics which are similar to those which employ monocrystals. Further, by connecting in parallel a plurality of such thin-film transistors it is possible to obtain characteristics which are effectively equivalent to those of a monocrystalline thin-film transistor in which the channel width has been increased.

Abstract: An SOI transistor has a self-aligned body contact formed through an extension to the gate, thereby forming the body contact with minimal increase in area and also avoiding the need to tie the source to the body, as in prior art schemes that passed the body contact through the source. The body contact aperture is formed by raising the source and drain to define an initial aperture, depositing a conformal layer that is etched to create aperture-defining sidewalls and etching the contact aperture using these sidewalls to define sidewall support members that support insulating sidewalls to isolate the collection electrode from both the gate and from the source and drain.