Abstract: A semiconductor memory device and a method of manufacturing the semiconductor memory device are provided. The semiconductor memory device includes a gate stacked structure with a cell array region and a contact region with a stepped shape, and a roughness of a first sidewall of the cell array region is greater than that of a second sidewall of the contact region.

Abstract: The present disclosure relates to a silicon carbide semiconductor device, and includes a p-type second well region provided as an upper layer portion of a semiconductor layer; an n-type second impurity region provided as an upper layer portion of the second well region; a p-type second well contact region provided as an upper layer portion of the second well region; a field insulating film provided on the second well region; a second contact passed through the field insulating film electrically connected to a first main electrode; a boundary gate insulating film provided on a boundary between the element region and the non-element region; a boundary gate electrode provided on the boundary gate insulating film; and a second main electrode. The second well contact region extends from below the second contact toward the element region, and the second impurity region extends from below the second contact toward the non-element region.

Abstract: A method of producing a polycrystalline silicon TFT includes forming nickel patterns on a substrate, forming a phosphorus doped silicon layer over the substrate and nickel patterns, and forming an intrinsic silicon layer on the phosphorus doped silicon layer. Alternatively, the intrinsic silicon layer can be formed on the substrate, the phosphorus doped silicon layer on the intrinsic silicon layer, and the nickel patterns on the phosphorus doped silicon layer. The structure is annealed to crystallize the phosphorus doped silicon and intrinsic silicon layers. A method of forming a crystalline silicon layer of a TFT device includes forming a first silicon film, forming a phosphorus doped silicon film on the first silicon film, forming a nickel film on the phosphorus doped silicon film, and annealing the structure to crystallize the phosphorus doped silicon and first silicon films. The first silicon and phosphorous doped silicon films are amorphous at formation.

Abstract: A method for producing an electrolytic capacitor includes: preparing an anode foil, a cathode foil, and a fibrous structure, the anode foil having a porous portion including a dielectric layer; preparing a conductive polymer-containing liquid, the conductive polymer-containing liquid containing a conductive polymer component and a first solvent; forming a separator by removing at least a part of the first solvent after applying the conductive polymer-containing liquid to the fibrous structure; forming a capacitor element from the anode foil, the separator, and the cathode foil; and impregnating the capacitor element with an electrolytic solution. An electrical conductivity of the electrolytic solution at 30° C. is 3.0 mS/cm or more.

Abstract: Disclosed are a memory device including a vertical stack structure, a method of manufacturing the same, and/or an electronic device including the memory device. The memory device including a vertical stack structure includes an oxygen scavenger layer on a base substrate, a recording material layer on the oxygen scavenger layer and in direct contact with the oxygen scavenger layer, a channel layer on the recording material layer, a gate insulating layer on the channel layer, and a gate electrode on the gate insulating layer. The oxygen scavenger layer includes an element that forms oxygen vacancies in the recording material layer and does not include oxygen.

Abstract: An interconnect fabrication method is disclosed herein that utilizes a disposable etch stop hard mask over a gate structure during source/drain contact formation and replaces the disposable etch stop hard mask with a dielectric feature (in some embodiments, dielectric layers having a lower dielectric constant than a dielectric constant of dielectric layers of the disposable etch stop hard mask) before gate contact formation. An exemplary device includes a contact etch stop layer (CESL) having a first sidewall CESL portion and a second sidewall CESL portion separated by a spacing and a dielectric feature disposed over a gate structure, where the dielectric feature and the gate structure fill the spacing between the first sidewall CESL portion and the second sidewall CESL portion. The dielectric feature includes a bulk dielectric over a dielectric liner. The dielectric liner separates the bulk dielectric from the gate structure and the CESL.

Abstract: Disclosed are a semiconductor device and an electronic system including the same. The semiconductor device may include a peripheral circuit structure including peripheral circuits that are on a semiconductor substrate, and first bonding pads that are electrically connected to the peripheral circuits, and a cell array structure including a memory cell array including memory cells that are three-dimensionally arranged on a semiconductor layer, and second bonding pads that are electrically connected to the memory cell array and are coupled to the first bonding pads. The cell array structure may include a resistor pattern positioned at the same level as the semiconductor layer, a stack including insulating layers and electrodes that are vertically and alternately stacked on the semiconductor layer, and vertical structures penetrating the stack.

Abstract: An image sensor includes a semiconductor substrate, a first isolation structure, a visible light detection structure, and an infrared light detection structure. The semiconductor substrate has a first surface and a second surface opposite to the first surface in a vertical direction. The first isolation structure is disposed in the semiconductor substrate for defining pixel regions in the semiconductor substrate. The visible light detection structure and the infrared light detection structure are disposed within the same pixel region, and a first portion of the visible light detection structure is disposed between the second surface of the semiconductor substrate and the infrared light detection structure in the vertical direction. The infrared light detection structure includes an epitaxial structure disposed in the semiconductor substrate, and the visible light detection structure includes a doped region including a material identical to a material of the semiconductor substrate.

Abstract: Gallium nitride-based monolithic microwave integrated circuits (MMICs) can comprise aluminum-based metals. Electrical contacts for gates, sources, and drains of transistors can include aluminum-containing metallic materials. Additionally, connectors, inductors, and interconnect devices can also comprise aluminum-based metals. The gallium-based MMICs can be manufactured in complementary metal oxide semiconductor (CMOS) facilities with equipment that produces silicon-based semiconductor devices.

Abstract: Methods for the manufacture of semiconductor devices with integrated two-dimensional (2D) materials are disclosed. Aspects can include forming a base structure comprising a seed material with a chemical element; forming source/drain contacts coupled to first and second portions of the base structure, respectively, wherein the source/drain contacts each have at least the chemical element; exposing a third portion of the base structure; selectively growing a 2D material at least coupled to the third portion of the base structure; and forming an active gate coupled to the 2D material.

Abstract: A system that includes an energy device having an active region configured to generate or consume electrical energy provided by an electrical current is discussed. A current limiter is disposed between the energy device and a current collector layer. The current limiter controls the current flow between the energy device and the current collector layer. A plurality of electrochemical transistors (ECTs) are arranged in an array such that each ECT in the array provides localized current control for the energy device. Each ECT includes a gate electrode, a drain electrode, a source electrode, and a channel disposed between the drain and the source electrodes. An electrolyte electrically couples the gate electrode to the channel such that an electrical signal at the gate electrode controls electrical conductivity of the channel. The current collector layer is a shared drain or source electrode for the ECTs.

Abstract: Provided are a solid-state imaging device, a manufacturing method thereof, and an electronic device that enable improvement of the sensitivity in a near infrared region by a simpler process. A solid-state imaging device includes a first semiconductor layer in which a first photoelectric conversion unit and a first floating diffusion are formed, a second semiconductor layer in which a second photoelectric conversion unit and a second floating diffusion are formed, and a wiring layer including a wiring electrically connected to the first and second floating diffusions. The first semiconductor layer and the second semiconductor layer are laminated, and the wiring layer is formed on a side of the first or second semiconductor layer, the side being opposite to a side on which the first semiconductor layer and the second semiconductor layer face each other.

Abstract: A display device includes display devices each including a display area and a non-display area adjacent to the display area, the display area of each of the display devices including a pixel, and a substrate on which each of the display devices is disposed. Each of the display devices includes a thin film transistor layer disposed on the substrate and including a thin film transistor, and a connection line electrically connected to the thin film transistor and disposed in the non-display area on the substrate. Connection lines of display devices adjacent to each other among the plurality of display devices are disposed staggered with respect to each other.

Abstract: A semiconductor device includes at least one first semiconductor element having a first electrode, a second semiconductor element having a second electrode, a first lead terminal connected to the first electrode of the at least one first semiconductor element, a second lead terminal connected to the second electrode of the second semiconductor element, a first resin with which the first lead terminal and the second lead terminal are sealed, and a second resin with which the at least one first semiconductor element and the second semiconductor element are sealed.

Abstract: A memory array comprises strings of memory cells. The memory array comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Channel-material-string constructions of memory cells extend through the insulative tiers and the conductive tiers. The channel material of the channel-material-string constructions is directly electrically coupled to conductor material of the conductor tier. Substructure material is in the conductor tier and spans laterally-across and laterally-between bottoms of multiple of the channel-material-string constructions. The substructure material is of different composition from an upper portion of the conductor material. The substructure material comprises laterally-opposing sides that taper laterally-inward moving deeper into the conductor tier. Other embodiments, including method, are disclosed.

Abstract: An organic semiconductor device with low driving voltage is provided. The organic semiconductor device includes a layer containing an organic compound between a pair of electrodes. The layer containing an organic compound includes a hole-transport region. The hole-transport region includes a first layer and a second layer. The first layer is positioned between the anode and the second layer. When a potential gradient of a surface potential of an evaporated film is set as GSP (mV/nm), a value obtained by subtracting GSP of an organic compound in the second layer from GSP of an organic compound in the first layer is less than or equal to 20 (mV/nm).

Abstract: A device includes a substrate including a first layer and a second layer. The first and second layers are positioned adjacent to each other and comprise a common boundary region extending from the first layer to the second layer. The first layer comprises graphite with a Bernal-crystal structure. The second layer comprises graphite with a rhombohedral crystal structure. The boundary region includes a border region having superconducting properties, namely; at a current density of 0 Ampere/m2 and a magnetic flux density of 0 Tesla exhibiting a critical temperature (Tc) which is higher than ?195° C., and/or at a temperature below the critical temperature (Tc) and a current density of 0 Ampere/m2, exhibiting a critical magnetic flux density (Bk) that is higher than 1 Tesla. The border region is coupled to an electric and/or a magnetic and/or an electromagnetic signal with a frequency greater than or equal to 0 Hertz.

Abstract: A structure of an asymmetric supercapacitor and a preparation method thereof is disclosed. In some implementations, the preparation comprises the steps of forming a polyaniline (PANI) nanowire on carbon cloth (CC) substrate (PANI/CC) by polymerization of an aniline, depositing a cobalt-nickel layer double hydroxides (CoNi-LDHs) on the PANI/CC by a hydrothermal process, and calcining of the cobalt-nickel layer double hydroxides (CoNi-LDHs) in the PANI/CC at a high temperature to form a metal carbide (CoC@NiC) on the carbon cloth. The structure of the asymmetric supercapacitor includes a metal carbide (CoC@NiC) as a positive electrode, a tungsten trioxide (WO3@C) as a negative electrode, and a poly (vinyl alcohol)/Potassium hydroxide (PVA/KOH) as an electrolyte gel.

Abstract: Aspects of the present disclosure are directed to systems and methods to reduce inductance on an integrated circuit package of a memory sub-system. A memory sub-system is also hereinafter referred to as a “memory device.” An example of a memory sub-system is a storage system, such as a SSD, and can be embodied as an integrated circuit package, including but not limited to a pin grid array (PGA), and ball grid array (BGA).

Abstract: In one embodiment, a semiconductor device includes a first substrate including first and second regions on its surface, a first control circuit on the first substrate in the first region, a first memory cell array above the first control circuit in the first region and connected to the first control circuit, and a first pad above the first memory cell array in the first region and connected to the first control circuit. The device further includes a second control circuit on the first substrate in the second region, a second memory cell array above the second control circuit in the second region and connected to the second control circuit, a second pad above the second memory cell array in the second region and connected to the second control circuit, and a connection line above the first and second memory cell arrays and connecting the first and second pads.