Patents Examined by Scott B. Geyer
  • Patent number: 10734528
    Abstract: A display panel with reduced power consumption is described. An example of the display panel includes an array of light emitting elements that are controllable to form an image, and a Thin-Film-Transistor (TFT) backplane comprising circuitry to drive the array of light emitting elements. The TFT backplane includes a plurality of field effect transistors (FETs). Each FET includes a source electrode, a drain electrode, a channel layer contacting the source electrode and the drain electrode, and a gate electrode adjacent to the channel layer and separated from the channel layer by an insulator. The channel layer includes a layer of metal phosphide.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: August 4, 2020
    Assignee: Intel Corporation
    Inventors: Khaled Ahmed, Dong Yeung Kwak, Ramon C. Cancel Olmo
  • Patent number: 10734604
    Abstract: A display device is provided. The display device includes a display panel including first and second display substrates that face each other, having an overlap area in which the first and second display substrates overlap with each other, and having a protruding area on one side of the overlap area, a sealing member between the first and second display substrates along edges of the overlap area, and at least one chamfered portion including a first chamfered portion, which is formed on at least one side of the protruding area, and a second chamfered portion, which is formed on the overlap area and adjacent to the first chamfered portion, wherein in the second chamfered portion, an end of the first display substrate is positioned beyond an end of the second display substrate.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: August 4, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hyun Min Hwang, Yong Kyu Jang, Jae Kyung Go, Dong Jo Kim, Young Min Kim, Chan Young Park, Dong Won Han
  • Patent number: 10734317
    Abstract: The invention relates to a method for embedding a discrete electronic device in a chip module. The chip module comprises a multilayer substrate which comprises a plurality of electrically conductive layers stacked above each other and an electrically non-conductive layer arranged between each pair of electrically conductive layers. The chip module is configured to receive one or more chips to be mounted onto a top surface thereof. Each electrically conductive layer comprises one or more electrically conductive structures. A recess is provided in a side surface of the chip module. The discrete electronic device is inserted into the recess. A first electrically conductive connection between a first electrical contact of the discrete electronic device and a first electrically conductive structure is established. Further, a second electrically conductive connection between a second electrical contact of the discrete electronic device and a second electrically conductive structure is established.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: August 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Andreas Huber, Harald Huels, Stefano S. Oggioni, Thomas Strach, Thomas-Michael Winkel
  • Patent number: 10720522
    Abstract: The invention relates to a device, named four-terminal switch, and a switching lattice comprising four-terminal switches. A four-terminal switch operates and can be fabricated according to the principles of complementary metal oxide semiconductor (CMOS) technology. However, it has four source/drain terminals as opposed to two terminals in conventional MOS devices; it is able to conduct current in two dimensions between four terminals as opposed to one-dimensional current flow in conventional MOS devices; and it is able to form dense switching lattice structures for area efficiency.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: July 21, 2020
    Assignee: ISTANBUL TEKNIK UNIVERSITESI
    Inventors: Mustafa Altun, Serzat Safaltin, Ismail Cevik
  • Patent number: 10718825
    Abstract: A magnetic field sensor includes a magnetic sense element and a shield structure formed on a substrate. The shield structure fully encircles the magnetic sense element for suppressing stray magnetic fields along a first axis and a second axis, both of which are parallel to a surface of the substrate and perpendicular to one another. A magnetic field is oriented along a third axis perpendicular to the surface of the substrate, and the magnetic sense element is configured to sense a magnetic field along the first axis. A magnetic field deflection element, formed on the substrate proximate the magnetic sense element, redirects the magnetic field from the third axis into the first axis to be sensed as a measurement magnetic field by the magnetic sense element. At least two magnetic field sensors, each fully encircled by a shield structure, form a gradient unit for determining a magnetic field gradient.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: July 21, 2020
    Assignee: NXP B.V.
    Inventors: Stephan Marauska, Jörg Kock, Hartmut Matz, Mark Isler, Dennis Helmboldt
  • Patent number: 10714345
    Abstract: A method for forming a junction in a germanium (Ge) layer of a substrate includes arranging the substrate in a processing chamber. The method includes performing a plasma pretreatment on the substrate in the processing chamber for a predetermined pretreatment period using a pretreatment plasma gas mixture including hydrogen gas species. The method includes supplying a doping plasma gas mixture to the processing chamber including a phosphorous (P) gas species and an antimony (Sb) gas species. The method includes striking plasma in the processing chamber for a predetermined doping period. The method includes annealing the substrate during a predetermined annealing period to form the junction in the germanium (Ge) layer.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: July 14, 2020
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Yunsang Kim, Hyuk-Jun Kwon
  • Patent number: 10714459
    Abstract: A light emitting device for a display includes a substrate and first, second, and third LED sub-units, a first transparent electrode between the first and second LED sub-units and in ohmic contact with the first LED sub-unit, a second transparent electrode between the second and third LED sub-units and in ohmic contact with the second LED sub-unit, a third transparent electrode between the second transparent electrode and the third LED sub-unit and in ohmic contact with the third LED sub-unit, at least one current spreader connected to at least one of the first, second, and third LED sub-units, electrode pads disposed on the substrate, and through-hole vias formed through the substrate, in which at least one of the through-hole vias is formed through the substrate and the first and second LED sub-units.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: July 14, 2020
    Assignee: Seoul Viosys Co., Ltd.
    Inventors: Chang Yeon Kim, Jong Hyeon Chae, Jong Min Jang, Ho Joon Lee, Seong Gyu Jang
  • Patent number: 10699977
    Abstract: A method of detecting delamination in an integrated circuit package structure, the method includes forming a plurality of through vias over a carrier substrate; placing a device die over the carrier substrate and between the through vias, wherein the device die comprises a metal pillar; forming a molding material surrounding the device die and the through vias; forming a testing metal line extending along a top surface of the molding material and past an interface between the device die and the molding material; applying a current to the testing metal line; detecting an electrical signal of the testing metal line during the applying the current to the testing metal line; and determining, based on the detected electrical signal of the testing metal line, whether a delamination occurs between the device die and the molding material.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: June 30, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yang-Che Chen, Tsung-Te Chou, Chen-Hua Lin, Huang-Wen Tseng, Chwen-Ming Liu
  • Patent number: 10689754
    Abstract: A charge storage cell includes a substrate having a back side conductive layer or conductive element, a top side metal pad coupled to the substrate, and an insulating layer formed on the metal pad. The metal pad will support an electric charge injected through the insulating layer by a charged particle beam. A regular array of charge storage cells provides a charge storage array.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: June 23, 2020
    Inventor: Peter C. Salmon
  • Patent number: 10692731
    Abstract: Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a base substrate having a first region and a second region; forming a first filling layer on the first region of the base substrate and a first hard mask layer on the first filling layer; performing a first treatment process on the second region of the base substrate using the first hard mask layer and the first filling layer as a mask; forming a second filling layer on the first region of the base substrate and a second mask on at least the second filling layer; removing the first hard mask layer and the first filling layer to expose the first region of the base substrate and to pattern the second hard mask layer on the second filling layer; and performing a second treatment process on the first region of the base substrate.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: June 23, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Cheng Long Zhang, Shi Liang Ji
  • Patent number: 10680003
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: June 9, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Zhenyu Lu, Jun Chen, Xiaowang Dai, Jifeng Zhu, Qian Tao, Yu Ru Huang, Si Ping Hu, Lan Yao, Li Hong Xiao, A Man Zheng, Kun Bao, Haohao Yang
  • Patent number: 10672747
    Abstract: A light emitting device for a display includes a substrate and first, second, and third LED sub-units, a first transparent electrode between the first and second LED sub-units and in ohmic contact with the first LED sub-unit, a second transparent electrode between the second and third LED sub-units and in ohmic contact with the second LED sub-unit, a third transparent electrode between the second transparent electrode and the third LED sub-unit and in ohmic contact with the third LED sub-unit, at least one current spreader connected to at least one of the first, second, and third LED sub-units, electrode pads disposed on the substrate, and through-hole vias formed through the substrate, in which at least one of the through-hole vias is formed through the substrate and the first and second LED sub-units.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: June 2, 2020
    Assignee: Seoul Viosys Co., Ltd.
    Inventors: Chang Yeon Kim, Jong Hyeon Chae, Jong Min Jang, Ho Joon Lee, Seong Gyu Jang
  • Patent number: 10672711
    Abstract: Embodiments of semiconductor structures including word line contact structures for three-dimensional memory devices and fabrication methods for forming word line contact structures are disclosed. The semiconductor structures include a staircase structure having a plurality of steps, and each step includes a conductive layer disposed over a dielectric layer. The semiconductor structures further include a barrier layer disposed over a portion of the conductive layer of each step. The semiconductor structures also include an etch-stop layer disposed on the barrier layer and an insulating layer disposed on the etch-stop layer. The semiconductor structures also include a plurality of conductive structures formed in the insulating layer and each conductive structure is formed on the conductive layer of each step.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: June 2, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Jifeng Zhu, Zhenyu Lu, Jun Chen, Si Ping Hu, Xiaowang Dai, Lan Yao, Li Hong Xiao, A Man Zheng, Kun Bao, Haohao Yang
  • Patent number: 10672898
    Abstract: Amorphous multi-component metallic films can be used to improve the performance of electronic devices such as resistors, diodes, and thin film transistors. An amorphous hot electron transistor (HET) having co-planar emitter and base electrodes provides electrical properties and performance advantages over existing vertical HET structures. Emitter and the base terminals of the transistor are both formed in an upper crystalline metal layer of an amorphous nonlinear resistor. The emitter and the base are adjacent to one another and spaced apart by a gap. The presence of the gap results in two-way Fowler-Nordheim tunneling between the crystalline metal layer and the amorphous metal layer, and symmetric I-V performance. Meanwhile, forming the emitter and base terminals in the same layer simplifies the HET fabrication process by reducing the number of patterning steps.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: June 2, 2020
    Assignee: Amorphyx, Incorporated
    Inventor: Sean William Muir
  • Patent number: 10665522
    Abstract: A semiconductor device and method is disclosed. Devices shown include a die coupled to an integrated routing layer, wherein the integrated routing layer includes a first width that is wider than the die. Devices shown further included a molded routing layer coupled to the integrated routing layer.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: May 26, 2020
    Assignee: Intel IP Corporation
    Inventors: Lizabeth Keser, Thomas Ort, Thomas Wagner, Bernd Waidhas
  • Patent number: 10658121
    Abstract: A capacitor and process for forming the capacitor, is provided wherein the capacitor comprises a conductive polymer layer. The conductive polymer comprises first particles comprising conductive polymer and polyanion and second particles comprising the conductive polymer and said polyanion wherein the first particles have an average particle diameter of at least 1 micron to no more than 10 microns and the second particles have an average particle diameter of at least 1 nm to no more than 600 nm.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: May 19, 2020
    Assignee: KEMET Electronics Corporation
    Inventors: Ajaykumar Bunha, Antony P. Chacko, Qingping Chen, Yaru Shi, Philip M. Lessner
  • Patent number: 10658293
    Abstract: A semiconductor device having a plurality of first wirings (X-direction) which include a first power supply line and a second power supply line, a plurality of third wirings (X-direction) which include a third (fourth) power supply line that is located above the first (second) power supply line and is electrically connected to the first (second) power supply line. The semiconductor device also has a plurality of second wirings (Y-direction) that include a first (second) connection wiring located above the first (second) power supply line and below the third (fourth) power supply line that is electrically connected to the first (second) power supply line and to the third (fourth) power supply line.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: May 19, 2020
    Assignee: SOCIONEXT INC.
    Inventor: Tomoyuki Kirimura
  • Patent number: 10658379
    Abstract: A method for forming a 3D memory device is disclosed. The method comprises: forming an alternating conductive/dielectric stack on a substrate; forming a slit vertically penetrating the alternating conductive/dielectric stack; forming an isolation layer on a sidewall of the slit; forming a first conductive layer covering the isolation layer; performing a plasma treatment followed by a first doping process to the first conductive layer; forming a second conductive layer covering the first conductive and filling the slit; performing a second doping process followed by a rapid thermal crystallization process to the second conductive layer; removing an upper portion of the first conductive layer and the second conductive layer to form a recess in the slit; and forming a third conductive layer in the recess.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: May 19, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Li Hong Xiao, Zhenyu Lu, Qian Tao, Lan Yao
  • Patent number: 10658584
    Abstract: An electrochemically actuatable electronic component comprises: a substrate; at least one first and one second actuating electrodes; at least one first and one second measuring electrodes; at least one storing electrode configured to free ions under the action of the actuating electrodes; at least one ionic conductor able to conduct the ions and that is located in a region placed between the measuring electrodes; a device suitable for: applying a voltage or a current between the first and second actuating electrodes to allow the migration of ions from the storing electrode to the first actuating electrode forming thereon an electrochemical deposition through the ionic conductor and for measuring, between the first and second measuring electrodes, a modification of at least one characteristic of the region placed between the first and second measuring electrodes, to determine at least one characteristic of the electronic component.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: May 19, 2020
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Sami Oukassi, Raphaël Salot
  • Patent number: 10651281
    Abstract: Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. A semiconductor layer is implanted over a first depth range of an inert gas species to modify the crystal structure of a semiconductor material of the semiconductor layer and form a first modified region. The semiconductor layer is annealed with a first annealing process to convert the semiconductor material within the first modified region to a non-single-crystal layer. The semiconductor layer is also implanted with ions of an element over a second depth range to modify the crystal structure of the semiconductor material of the semiconductor layer and form a second modified region containing a concentration of the element. The semiconductor layer is annealed with a second annealing process to convert the semiconductor material within the second modified region to an insulator layer containing the element.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: May 12, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Siva P. Adusumilli, John J. Ellis-Monaghan, Anthony K. Stamper, Ian McCallum-Cook, Mark Goldstein