Patents Examined by Scott B. Geyer
  • Patent number: 10297525
    Abstract: A base plate for a heat sink as well as a heat sink and an IGBT module having the same are provided. The base plate includes: a base plate body, including a body part; and a first surface layer and a second surface layer disposed respectively on two opposing surfaces of the body part; and N pins disposed on the first surface layer and spaced apart from one another, each pin having a first end fixed on the first surface layer and a second end configured as a free end, in which the first surface layer and the N pins are configured to contact a coolant, an area of a first portion of the first surface layer contacting the coolant is denoted as S1, and an area of a second portion of the first surface layer contacting each pin is denoted as S2, in which 180?S1/S2?800, and 300?N<650.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: May 21, 2019
    Assignee: BYD COMPANY LIMITED
    Inventors: Qing Gong, Yaxuan Sun, Xinping Lin, Shuming Zhao, Bo Wu, Jingjing Luo, Donghai Cheng
  • Patent number: 10287458
    Abstract: A laminate includes, sequentially and adjacent to each other: a first base material; a temporary adhesion film; and a second base material, in which the tensile elastic modulus E of the temporary adhesion film at 25° C. in conformity with JIS K 7161:1994 is in a range of 25 to 2000 MPa. A base material is peeled off by fixing any one of the first base material and the second base material of the laminate at 25° C. and pulling an end portion of the other base material up in a direction perpendicular to the surface of the other base material from an interface with the temporary adhesion film at a speed of 50 mm/min, and the force applied during the pulling is measured using a force gauge and the value is 0.33 N/mm or less.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: May 14, 2019
    Assignee: FUJIFILM Corporation
    Inventors: Yoshitaka Kamochi, Yu Iwai, Mitsuru Sawano, Ichiro Koyama, Atsushi Nakamura
  • Patent number: 10283439
    Abstract: A fan-out semiconductor package includes: a first connection member having a through-hole and having a passive component disposed in the first connection member; a semiconductor chip disposed in the through-hole of the first connection member and having an active surface having connection pads disposed therein and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; and a second connection member disposed on the first connection member and the active surface of the semiconductor chip. The first connection member and the second connection member include, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip, and the passive component is electrically connected to the connection pads of the semiconductor chip through the redistribution layer of the second connection member.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: May 7, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jung Hyun Cho, Yong Ho Baek, Jun Oh Hwang, Joo Hwan Jung, Moon Hee Yi
  • Patent number: 10274169
    Abstract: The present techniques are related to an apparatus for an MEMS LED zoom. The apparatus for includes an LED light source and a collimation lens. The collimation lens to collimate light from the LED light source. The apparatus is also to include an active lens. The active lens to adjust the collimated light from the collimation lens.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: April 30, 2019
    Assignee: Intel Corporation
    Inventor: Mikko Ollila
  • Patent number: 10276704
    Abstract: A high electron mobility transistor includes a semiconductor structure having a channel layer and a cap layer forming a two dimensional electron gas (2-DEG) channel, and a source, a drain, and a gate electrodes. The gate is arranged on the cap layer between the source and the drains, such that the conductivity of the 2-DEG channel is modulated in response to applying voltage to the gate. The cap layer includes III-N material. The gate has a layered structure including a bottom metal layer arranged on cap layer, a ferroelectric oxide (FEO) layer arranged on bottom metal layer, and a top metal layer arranged on the FEO layer. Thickness of FEO layer is less than tcap/(2??cap), wherein ? is a parameter of material of FEO layer, tcap is thickness of cap layer, and ?cap is electric permittivity of cap layer.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: April 30, 2019
    Assignee: Mitsubishi Electric Research Laboratiories, Inc.
    Inventors: Koon Hoo Teo, Nadim Chowdhury
  • Patent number: 10269966
    Abstract: A semiconductor device including a Fin FET device includes a fin structure extending in a first direction and protruding from a substrate layer. The fin structure includes a bulk stressor layer formed on the substrate layer and a channel layer disposed over the bulk stressor layer. An oxide layer is formed on the substrate layer extending away from the channel layer. A source-drain (SD) stressor structure is disposed on sidewalls of the channel layer over the oxide layer. A gate stack including a gate electrode layer and a gate dielectric layer covers a portion of the channel layer and extends in a second direction perpendicular to the first direction.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: April 23, 2019
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Chao-Hsin Chien, Chi-Wen Liu, Chen-Han Chou
  • Patent number: 10269790
    Abstract: A semiconductor device includes a substrate and a field effect transistor (FET) arranged on the substrate. The FET includes a gate positioned on the substrate. The gate includes a nanosheet extending through a channel region of the gate. The FET includes a pair of source/drains arranged on opposing sides of the gate. The semiconductor device further includes a bipolar junction transistor (BJT) arranged adjacent to the FET on the substrate. The BJT includes an emitter and a collector. The BJT includes a nanosheet including a semiconductor material extending from the emitter to the collector, with a doped semiconductor material arranged above and below the nanosheet.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: April 23, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li, Geng Wang, Qintao Zhang
  • Patent number: 10262881
    Abstract: Embodiments of an enclosed coating system according to the present teachings can be useful for patterned area coating of substrates in the manufacture of a variety of apparatuses and devices in a wide range of technology areas, for example, but not limited by, OLED displays, OLED lighting, organic photovoltaics, Perovskite solar cells, and organic semiconductor circuits. Enclosed and environmentally controlled coating systems of the present teachings can provide several advantages, such as: 1) Elimination of a range of vacuum processing operations such coating-based fabrication can be performed at atmospheric pressure. 2) Controlled patterned coating eliminates material waste, as well as eliminating additional processing typically required to achieve patterning of an organic layer. 3) Various formulations used for patterned coating with various embodiments of an enclosed coating apparatus of the present teachings can have a wide range of physical properties, such as viscosity and surface tension.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: April 16, 2019
    Assignee: Kateeva, Inc.
    Inventors: Conor F. Madigan, Alexander Sou-Kang Ko, Eliyahu Vronsky
  • Patent number: 10263138
    Abstract: The present invention provides a micro light-emitting-diode display panel and a manufacturing method thereof. The micro light-emitting-diode display panel which presses and fixes the micro light-emitting-diodes into a resin adhesive layer by filling the resin adhesive layer in the pixel groove. Meanwhile, the electrode at the bottom of the micro light-emitting-diode is guided to the top of the micro light-emitting-diode by the connection electrode, making the two electrodes of the micro light-emitting-diode are at the top, to facilitate the connection between the electrodes of the micro light-emitting-diode and the electrode points, which can reduce the difficulty of the electrode bonding of the micro light-emitting-diode, and improve the reliability of the electrode bonding of the micro light-emitting-diode.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: April 16, 2019
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Macai Lu
  • Patent number: 10254574
    Abstract: Provided is a display device having a flexible substrate including an active region and a wiring region. The active region possesses a plurality of pixels each including a display element. The wiring region has a plurality of terminals, and a plurality of wirings extends from the active region to the plurality of terminals. An insulating film included in the active region and extending from the active region has a sidewall between an edge of the flexible substrate and the wiring adjacent to the edge in the wiring region. The sidewall has a curved portion on a plane in which the plurality of wirings is arranged, and a distance between the edge and the curved portion is curvedly varied.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: April 9, 2019
    Assignee: Japan Display Inc.
    Inventor: Naoki Tokuda
  • Patent number: 10256288
    Abstract: A nonvolatile memory device can be manufactured without adding any major modification to a structure and component elements of a conventional MOS type silicon device, and is realized without deteriorating an electrical characteristic of an insulating-film/semiconductor interface and on the basis of a new operational principle. The nonvolatile memory device 10 is a capacitor configured by a metal electrode 16, two kinds of insulating films 13 and 15, and an interface structure of an insulating film 12/semiconductor 11, and has a MIS structure of providing a monolayer-level O-M1-O layer 14 to an insulating-film 13/semiconductor 15 interface. The nonvolatile memory device 10 realizes a nonvolatile information storage operation by changing strength or polarities of interface dipoles induced near the O-M1-O layer 14 through electrical stimulation applied from a gate electrode.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: April 9, 2019
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventor: Noriyuki Miyata
  • Patent number: 10256310
    Abstract: A split-gate flash memory cell is provided. The split-gate flash memory cell includes a semiconductor substrate having a source region and a drain region. The source region and the drain region are separated by a channel region. The split-gate flash memory cell also includes a concave trench in the semiconductor substrate, a floating gate dielectric lining the concave trench, and a floating gate situated in the concave trench on the floating gate dielectric. The floating gate has a convex bottom surface. The split-gate flash memory cell also includes an inter-gate dielectric on the floating gate, and a control gate on the inter-gate dielectric.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: April 9, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Manoj Kumar, Ankit Kumar, Chia-Hao Lee, Chih-Cherng Liao
  • Patent number: 10256220
    Abstract: An optical sensor that captures a heart rate and/or a blood oxygen content includes a light source including a light emitter that emits electromagnetic radiation with a first wavelength range including green light, a second wavelength range including red light and a third wavelength range including infrared radiation, and three light detectors, each including a filter for electromagnetic radiation, wherein a first filter is transmissive for light of the first wavelength range and non-transmissive for light of the second wavelength range and the infrared radiation of the third wavelength range, a second filter is transmissive for light of the second wavelength range and non-transmissive for light of the first wavelength range and the infrared radiation of the third wavelength range and a third filter is transmissive for the infrared radiation of the third wavelength range and non-transmissive for light of the first and the second wavelength range.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: April 9, 2019
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: David O'Brien, Tim Böscke, Sebastian Pielnhofer
  • Patent number: 10256380
    Abstract: A method of producing an optoelectronic component includes embedding an optoelectronic component part into a molded body such that an upper side of the optoelectronic component part is at least partially exposed on an upper side of the molded body; arranging and structuring a sacrificial layer above the upper side of the optoelectronic component part and the upper side of the molded body; arranging and structuring a layer of an optical material above the sacrificial layer; and removing the sacrificial layer.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: April 9, 2019
    Assignee: OSRAM Opto Seiconductors GmbH
    Inventors: Wolfgang Moench, Frank Singer, Thomas Schwarz, Jürgen Moosburger, Stefan Illek
  • Patent number: 10249727
    Abstract: In order to improve the characteristics of a semiconductor device including: a channel layer and a barrier layer formed above a substrate; and a gate electrode arranged over the barrier layer via a gate insulating film, the semiconductor device is configured as follows. A silicon nitride film is provided over the barrier layer between a source electrode and the gate electrode, and is also provided over the barrier layer between a drain electrode and the gate electrode GE. The surface potential of the barrier layer is reduced by the silicon nitride film, thereby allowing two-dimensional electron gas to be formed. Thus, by selectively forming two-dimensional electron gas only in a region where the silicon nitride film is formed, a normally-off operation can be performed even if a trench gate structure is not adopted.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: April 2, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yasuhiro Okamoto
  • Patent number: 10242909
    Abstract: A method for forming a conductive structure for a semiconductor device includes depositing a barrier layer in a trench formed in a dielectric material and forming an interface layer over the barrier layer. A main conductor is formed over the interface layer, and the main conductor is recessed selectively to the interface layer and the barrier layer to a position below a top surface of the dielectric layer. The interface layer is selectively wet etched to the main conductor and the barrier layer using a chemical composition having an oxidizer, wherein the chemical composition is buffered to include a pH above 7. The barrier layer is selectively etching to the main conductor and the interface layer.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: March 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin D. Briggs, Cornelius B. Peethala, David L. Rath
  • Patent number: 10236251
    Abstract: An antifuse structure including a first electrode that is present in at a base of the opening in the dielectric material. The antifuse structure further includes an antifuse material layer comprising a phase change material alloy of tantalum and nitrogen. A first surface of the antifuse material layer is present in direct contact with the first electrode. A second electrode is present in direct contact with a second surface of the antifuse material layer that is opposite the first surface of the antifuse material layer.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: March 19, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Chih-Chao Yang
  • Patent number: 10236219
    Abstract: Forming a PFET work function metal layer on a p-type field effect transistor (PFET) fin in a PFET region and on an n-type field effect transistor (NFET) fin in an NFET region, removing a portion of the PFET work function metal layer between the PFET fin and the NFET fin, thinning the PFET work function metal layer, patterning an organic planarization layer on the PFET work function metal layer, where the organic planarization layer covers the PFET region and partially covers the NFET region, removing the PFET work function metal layer in the NFET region, by etching isotropically selective to the organic planarization layer and an insulator in the NFET region, removing the organic planarization layer, and conformally forming an NFET work function metal layer on the semiconductor structure.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: March 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Ruqiang Bao, Kangguo Cheng, Hemanth Jagannathan, Choonghyun Lee, Junli Wang
  • Patent number: 10236389
    Abstract: A miniaturized transistor is provided. A first layer is formed over a third insulator over a semiconductor; a second layer is formed over the first layer; an etching mask is formed over the second layer; the second layer is etched using the etching mask until the first layer is exposed to form a third layer; a selective growth layer is formed on a top surface and a side surface of the third layer; the first layer is etched using the third layer and the selective growth layer until the third insulator is exposed to form a fourth layer; and the third insulator is etched using the third layer, the selective growth layer, and the fourth layer until the semiconductor is exposed to form a first insulator.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: March 19, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuta Endo, Hideomi Suzawa, Sachiaki Tezuka, Tetsuhiro Tanaka, Toshiya Endo, Mitsuhiro Ichijo
  • Patent number: 10236250
    Abstract: An antifuse structure including a first electrode that is present in at a base of the opening in the dielectric material. The antifuse structure further includes an antifuse material layer comprising a phase change material alloy of tantalum and nitrogen. A first surface of the antifuse material layer is present in direct contact with the first electrode. A second electrode is present in direct contact with a second surface of the antifuse material layer that is opposite the first surface of the antifuse material layer.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: March 19, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Chih-Chao Yang