Patents Examined by Scott B. Geyer
  • Patent number: 11127717
    Abstract: In one embodiment, a semiconductor device includes a first substrate including first and second regions on its surface, a first control circuit on the first substrate in the first region, a first memory cell array above the first control circuit in the first region and connected to the first control circuit, and a first pad above the first memory cell array in the first region and connected to the first control circuit. The device further includes a second control circuit on the first substrate in the second region, a second memory cell array above the second control circuit in the second region and connected to the second control circuit, a second pad above the second memory cell array in the second region and connected to the second control circuit, and a connection line above the first and second memory cell arrays and connecting the first and second pads.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: September 21, 2021
    Assignee: Toshiba Memory Corporation
    Inventor: Tomoya Sanuki
  • Patent number: 11127624
    Abstract: A semiconductor on insulator type structure, which may be used for a front side type imager, successively comprises, from its rear side to its front side, a semiconductor support substrate, an electrically insulating layer and an active layer comprising a monocrystalline semiconductor material. The active layer is made of a semiconductor material having a state of mechanical stress with respect to the support substrate, and the support substrate comprises, on its rear side, a silicon oxide layer, the thickness of the oxide layer being chosen to compensate bow induced by the mechanical stress between the active layer and the support substrate during cooling of the structure after the formation by epitaxy of at least a part of the active layer on the support substrate.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: September 21, 2021
    Assignee: Soitec
    Inventors: Walter Schwarzenbach, Oleg Kononchuk, Ludovic Ecarnot
  • Patent number: 11127737
    Abstract: A number of monolithic diode limiter semiconductor structures are described. The diode limiters can include a hybrid arrangement of diodes with different intrinsic regions, all formed over the same semiconductor substrate. In one example, two PIN diodes in a diode limiter semiconductor structure have different intrinsic region thicknesses. The first PIN diode has a thinner intrinsic region, and the second PIN diode has a thicker intrinsic region. This configuration allows for both the thin intrinsic region PIN diode and the thick intrinsic region PIN diode to be individually optimized. The thin intrinsic region PIN diode can be optimized for low level turn on and flat leakage, and the thick intrinsic region PIN diode can be optimized for low capacitance, good isolation, and high incident power levels. This configuration is not limited to two stage solutions, as additional stages can be used for higher incident power handling.
    Type: Grant
    Filed: February 12, 2020
    Date of Patent: September 21, 2021
    Assignee: MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC.
    Inventors: James Joseph Brogle, Joseph Gerard Bukowski, Margaret Mary Barter, Timothy Edward Boles
  • Patent number: 11114478
    Abstract: A thin film transistor and a manufacture method thereof, an array substrate and a manufacture method thereof are provided. The manufacture method of the thin film transistor includes: providing a base substrate; and forming a gate electrode, a first electrode, a second electrode and a semiconductor layer of the thin film transistor on the base substrate. At least one of the gate electrode, the first electrode and the second electrode includes N portions that are stacked in a direction perpendicular to the base substrate, adjacent two of the N portions are in direct contact with each other, and N is a positive integer more than or equal to 2. The method includes: performing N patterning processes to respectively form the N portions.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: September 7, 2021
    Assignees: Hefei Xinsheng Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventor: Leilei Cheng
  • Patent number: 11114392
    Abstract: A wireless communication device that includes a first electrode connected to a first terminal electrode of an RFIC element and a second electrode connected to a second terminal electrode of the RFIC element. Moreover, the first electrode has a longitudinal direction and a lateral direction and has a first portion connected to the first terminal electrode and a second portion that faces the first portion and the second electrode. The first portion has an extended portion that extends in the longitudinal direction beyond a connection point between the second electrode and the second terminal electrode.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: September 7, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Noboru Kato
  • Patent number: 11107966
    Abstract: A quantum computing device is fabricated by forming, on a superconductor layer, a first resist pattern defining a device region and a sensing region within the device region. The superconductor layer within the sensing region is removed, exposing a region of a first surface of an underlying semiconductor layer outside the device region. The exposed region of the semiconductor layer is implanted, forming an isolation region surrounding the device region. The sensing region and a portion of the device region of the superconductor layer are exposed. A sensing region contact is formed by coupling the first surface of the semiconductor layer with a first metal layer. A nanorod contact using the first metal within the portion of the device region outside the sensing region is formed. By depositing a second metal layer on a second surface of the semiconductor layer within the sensing region, a tunnel junction gate is formed.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: August 31, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven J. Holmes, Stephen W. Bedell, Sean Hart, Devendra K. Sadana, Ning Li, Patryk Gumann
  • Patent number: 11107965
    Abstract: A quantum computing device is fabricated by forming, on a superconductor layer, a first resist pattern defining a device region and a sensing region within the device region. The superconductor layer within the sensing region is removed, exposing a region of an underlying semiconductor layer outside the device region. The exposed region of the semiconductor layer is implanted, forming an isolation region surrounding the device region. Using an etching process subsequent to the implanting, the sensing region and a portion of the device region of the superconductor layer adjacent to the isolation region are exposed. By depositing a first metal layer within the sensing region, a tunnel junction gate is formed. A sensing region gate is formed by coupling the semiconductor layer with a second metal layer. A nanorod contact using the second metal within the portion of the device region outside the sensing region is formed.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: August 31, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven J. Holmes, Devendra K. Sadana, Sean Hart, Stephen W. Bedell, Ning Li, Patryk Gumann
  • Patent number: 11101276
    Abstract: Embodiments of semiconductor structures including word line contact structures for three-dimensional memory devices and fabrication methods for forming word line contact structures are disclosed. The semiconductor structures include a staircase structure having a plurality of steps, and each step includes a conductive layer disposed over a dielectric layer. The semiconductor structures further include a barrier layer disposed over a portion of the conductive layer of each step. The semiconductor structures also include an etch-stop layer disposed on the barrier layer and an insulating layer disposed on the etch-stop layer. The semiconductor structures also include a plurality of conductive structures formed in the insulating layer and each conductive structure is formed on the conductive layer of each step.
    Type: Grant
    Filed: May 1, 2020
    Date of Patent: August 24, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Jifeng Zhu, Zhenyu Lu, Jun Chen, Si Ping Hu, Xiaowang Dai, Lan Yao, Li Hong Xiao, A Man Zheng, Kun Bao, Haohao Yang
  • Patent number: 11101215
    Abstract: The various embodiments described herein include methods, devices, and circuits for reducing or minimizing current crowding effects in manufactured superconductors. In some embodiments, a superconducting circuit includes: (1) a first component having a first connection point, the first connection point having a first width; (2) a second component having a second connection point, the second connection point having a second width that is larger than the first width; and (3) a connector electrically connecting the first connection point and the second connection point, the connector including: (a) a first taper having a first slope and a non-linear shape; (b) a second taper having a second slope; and (c) a connecting portion connecting the first taper to the second taper, the connecting portion having a third slope that is less than the first slope and less than the second slope.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: August 24, 2021
    Assignee: PSIQUANTUM CORP.
    Inventors: Faraz Najafi, Vitor Riseti Manfrinato
  • Patent number: 11094532
    Abstract: There is provided a technique that includes forming a film containing silicon, oxygen, carbon, and nitrogen on a substrate by performing a cycle a predetermined number of times, the cycle including: forming a first layer containing silicon, carbon, and nitrogen by performing a set a predetermined number of times, the set including: supplying a first precursor, which contains at least two Si—N bonds and at least one Si—C bond in one molecule, to the substrate; and supplying a second precursor, which contains nitrogen and hydrogen, to the substrate; and forming a second layer by supplying an oxidant to the substrate, to thereby oxidize the first layer.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: August 17, 2021
    Assignee: Kokusai Electric Corporation
    Inventors: Atsushi Sano, Kimihiko Nakatani, Tatsuru Matsuoka, Kenji Kameda, Satoshi Shimamoto
  • Patent number: 11081440
    Abstract: An interposer includes: a base substrate; an interconnection structure on a top surface of the base substrate and including a metal interconnection pattern; an upper passivation layer on the interconnection structure and having compressive stress; a lower passivation layer under a bottom surface of base substrate, the lower passivation layer having compressive stress that is less than the compressive stress of the upper passivation layer; a lower conductive layer under the lower passivation layer; and a through electrode penetrating the base substrate and the lower passivation layer. The through electrode electrically connects the lower conductive layer to the metal interconnection pattern of the interconnection structure.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: August 3, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yu-Kyung Park, Seung-kwan Ryu, Min-seung Yoon, Yun-seok Choi
  • Patent number: 11081631
    Abstract: An asymmetrically shaped chip-scale packaging (CSP) light-emitting device (LED) includes an LED chip, a photoluminescent structure (or a light-transmitting structure), and a reflective structure. The photoluminescent structure covers the upper surface and/or the edge surface of the LED chip; and the reflective structure at least partially covers the edge surface of the photoluminescent structure. The reflective structure partially reflects the primary light emitted from the edge surface of the LED chip or the converted secondary light radiated from the edge surface of the photoluminescent structure, therefore shaping the radiation pattern asymmetrically.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: August 3, 2021
    Assignee: Maven Optronics Co., LTD.
    Inventors: Chieh Chen, Chia-Hsien Chang
  • Patent number: 11081286
    Abstract: A method for manufacturing an electrolytic capacitor includes a first step, a second step, and a third step. In the first step, a capacitor element is formed. The capacitor element includes an anode body, a cathode body, and a separator. The anode body includes a dielectric layer formed on a surface of the anode body. And the separator is disposed between the anode body and the cathode body. In the second step, the capacitor element is impregnated with a treatment solution containing an acid component and a base component. In the third step, the capacitor element is, after the second step, impregnated with a conductive polymer dispersion in a state that a part of the treatment solution remains in the capacitor element. The conductive polymer dispersion is obtained by dispersing, in a solvent, conductive polymer particles each including polyanion. A pH of the treatment solution is higher than a pH of the conductive polymer dispersion.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: August 3, 2021
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shumpei Matsushita, Tomoyuki Tashiro, Takayuki Matsumoto, Tatsuji Aoyama
  • Patent number: 11081466
    Abstract: A method for joining a microelectronic chip to at least one wire element comprises a first step of applying a cover to a first face of the microelectronic chip, the cover being configured to form, with the first face, at least one temporary side groove. The method additionally comprises a step of inserting the wire element into the temporary groove. The method further comprises a step of attaching the wire element to the microelectronic chip. The method additionally comprises a step of removing the cover from the microelectronic chip.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: August 3, 2021
    Assignee: PRIMO1D
    Inventors: Delphine Rolland, Christopher Mackanic, Gianfranco Andia Vera, Emmanuel Arene
  • Patent number: 11075146
    Abstract: Microfeature workpieces having alloyed conductive structures, and associated methods are disclosed. A method in accordance with one embodiment includes applying a volume of material to a bond pad of a microfeature workpiece, with the volume of material including a first metallic constituent and the bond pad including a second constituent. The method can further include elevating a temperature of the volume of material while the volume of material is applied to the bond pad to alloy the first metallic constituent and the second metallic constituent so that the first metallic constituent is alloyed generally throughout the volume of material. A thickness of the bond pad can be reduced from an initial thickness T1 to a reduced thickness T2.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: July 27, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Rick C. Lake, William M. Hiatt
  • Patent number: 11075078
    Abstract: A method for making a semiconductor device may include forming an isolation region adjacent an active region in a semiconductor substrate, and selectively etching the active region so that an upper surface of the active region is below an adjacent surface of the isolation region and defining a stepped edge therewith. The method may further include forming a superlattice overlying the active region. The superlattice may include stacked groups of layers, with each group of layers comprising stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: July 27, 2021
    Assignee: ATOMERA INCORPORATED
    Inventors: Nyles Wynn Cody, Keith Doran Weeks, Robert John Stephenson, Richard Burton, Yi-Ann Chen, Dmitri Choutov, Hideki Takeuchi, Yung-Hsuan Yang
  • Patent number: 11069799
    Abstract: Amorphous multi-component metallic films can be used to improve the performance of electronic devices such as resistors, diodes, and thin film transistors. An amorphous hot electron transistor (HET) having co-planar emitter and base electrodes provides electrical properties and performance advantages over existing vertical HET structures. Emitter and the base terminals of the transistor are both formed in an upper crystalline metal layer of an amorphous nonlinear resistor. The emitter and the base are adjacent to one another and spaced apart by a gap. The presence of the gap results in two-way Fowler-Nordheim tunneling between the crystalline metal layer and the amorphous metal layer, and symmetric I-V performance. Meanwhile, forming the emitter and base terminals in the same layer simplifies the HET fabrication process by reducing the number of patterning steps.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: July 20, 2021
    Assignee: Amorphyx, Incorporated
    Inventor: Sean William Muir
  • Patent number: 11063157
    Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a pillar structure abutting a trench capacitor. A substrate has sidewalls that define a trench. The trench extends into a front-side surface of the substrate. The trench capacitor includes a plurality of capacitor electrode layers and a plurality of capacitor dielectric layers that respectively line the trench and define a cavity within the substrate. The pillar structure is disposed within the substrate. The pillar structure has a first width and a second width less than the first width. The first width is aligned with the front-side surface of the substrate and the second width is aligned with a first point disposed beneath the front-side surface.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: July 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Li Cheng, Jyun-Ying Lin, Alexander Kalnitsky, Shih-Fen Huang, Shu-Hui Su, Ting-Chen Hsu, Tuo-Hsin Chien, Felix Ying-Kit Tsui, Shi-Min Wu, Yu-Chi Chang
  • Patent number: 11056285
    Abstract: A capacitor comprising a solid electrolytic capacitor element that contains a sintered porous anode body, a dielectric that overlies the anode body, and a solid electrolyte is provided. The solid electrolyte contains an interior conductive polymer layer overlying the dielectric, an adhesive film that overlies the interior conductive polymer layer, which may be formed by sequential vapor deposition. An exterior conductive polymer layer also overlies the adhesive film.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: July 6, 2021
    Assignee: AVX Corporation
    Inventors: Jan Petrzilek, Mitchell D. Weaver, Miloslav Uher
  • Patent number: 11056634
    Abstract: Josephson magnetic memory cells with a semiconductor-based magnetic spin valve are described. An example memory cell includes a first superconducting electrode, a second superconducting electrode, and a semiconductor-based magnetic spin valve arranged between the two superconducting electrodes. The semiconductor-based magnetic spin valve includes a semiconductor layer and a first ferromagnetic insulator arranged near the semiconductor layer, arranged on a first side of the semiconductor layer, configured to provide a fixed magnetization oriented in a first direction.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: July 6, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Roman Lutchyn, Andrey Antipov