Abstract: An integrated circuit die has a layer of first semiconductor material comprising a Group III element and nitrogen and having a first bandgap. A first transistor structure on a first region of the die has: a quantum well (QW) structure that includes at least a portion of the first semiconductor material and a second semiconductor material having a second bandgap smaller than the first bandgap, a first source and a first drain in contact with the QW structure, and a gate structure in contact with the QW structure between the first source and the first drain. A second transistor structure on a second region of the die has a second source and a second drain in contact with a semiconductor body, and a second gate structure in contact with the semiconductor body between the second source and the second drain. The semiconductor body comprises a Group III element and nitrogen.

Abstract: The present technology relates to a light-receiving element and a distance measurement module. A light-receiving element includes: a first voltage application unit to which a voltage is applied; a first charge detection unit that is disposed at a periphery of the first voltage application unit; a second voltage application unit to which a voltage is applied; a second charge detection unit that is disposed at a periphery of the second voltage application unit; a third voltage application unit to which a first voltage is applied; and a voltage control unit that applies a second voltage to one of the first voltage application unit and the second a voltage application unit and causes the other to be in a floating state, the second voltage being different from the first voltage. The present technology is applicable to a light-receiving element.

Abstract: Provided is a solid-state imaging unit that includes a stacked structure including a sensor substrate and a circuit board. The sensor board has an effective pixel region where an imaging device is disposed. The imaging device includes a plurality of pixels and is configured to receive external light in each of the pixels to generate a pixel signal. The circuit board includes a chip including a first portion and a second portion that are integrated with each other. The first portion includes a signal processing circuit that performs signal processing of the pixel signal. The second portion is disposed at a position different from a position of the first portion in an in-plane direction. Here, both the first portion and the second portion are disposed to overlap the effective pixel region in a stacking direction of the sensor board and the circuit board.

Abstract: A photoelectric conversion apparatus includes a first and a second multilayer wiring layer. The first or the second multilayer wiring layer is provided with a first electrode supplied with a first voltage from an outside of the photoelectric conversion apparatus. The first electrode is not connected with a second semiconductor layer.

Abstract: Implementations of methods of singulating a plurality of die included in a substrate may include exposing a substrate material of a substrate in a die street through removing a metal layer in the die street coupled to the substrate, wherein only a portion of the substrate material in the die street is removed, and singulating a plurality of die included in the substrate through plasma etching the exposed substrate material of the substrate in the die street.

Abstract: An image sensing device is disclosed. The image sensing device includes a first unit pixel provided with a first photoelectric conversion element and a first floating diffusion region, a second unit pixel provided with a second photoelectric conversion element and a second floating diffusion region, a third unit pixel provided with a third photoelectric conversion region and a third floating diffusion region, and a fourth unit pixel provided with a fourth photoelectric conversion element and a fourth floating diffusion region. The first to fourth unit pixels are isolated from each other by a first device isolation structure. The first to fourth floating diffusion regions are coupled to a common floating diffusion node through conductive lines.

Abstract: A display module and a manufacturing method thereof are provided. The manufacturing method may include forming an epitaxial film comprising a light emitting layer, a first type semiconductor layer, and a second type semiconductor layer, attaching the epitaxial film to an intermediate substrate comprising a conductive material, patterning the epitaxial film to form a light emitting diode (LED) and coupling the LED to a driving circuit layer through the conductive material.

Abstract: An antenna comprising; a substrate; a continuous film of yttrium barium copper oxide (YBCO) disposed on the substrate having first and second regions, wherein the first region has a first oxygen doping level and wherein the second region has a second oxygen doping level that is different from the first oxygen doping level; a nano-scale conductive structure, shaped to resonate at a terahertz (THz) frequency, disposed on a boundary between the first and second regions; and a conductive path electrically connected to the first and second regions and to the conductive structure such that induced current in the structure due to incoming THz radiation heats the boundary thereby creating a thermal gradient, which results in the generation of Seebeck effect voltage.

Abstract: The present disclosure relates to an integrated chip structure having a first copper pillar disposed over a metal pad of an interposer substrate. The first copper pillar has a sidewall defining a recess. A nickel layer is disposed over the first copper pillar and a solder layer is disposed over the first copper pillar and the nickel layer. The solder layer continuously extends from directly over the first copper pillar to within the recess. A second copper layer is disposed between the solder layer and a second substrate.

Abstract: An integrated circuit structure comprises a base layer that includes a channel region, wherein the base layer and the channel region include group III-V semiconductor material. A polarization layer stack is over the base layer, wherein the polarization layer stack comprises a buffer stack, an interlayer over the buffer stack, a polarization layer over the interlayer. A cap layer stack is over the polarization layer to reduce transistor access resistance.

Abstract: A method of soldering elements together includes providing a substrate having a metal die attach surface, providing a semiconductor die that is configured as a power semiconductor device and having a semiconductor body, a rear side metallization, and a front side layer stack, the front side layer stack having a front side metallization and a contaminant protection layer, arranging the semiconductor die on the substrate with a region of solder material between the die attach surface and the rear side metallization, and performing a soldering process that reflows the region of solder material to form a soldered joint between the metal die attach surface and the rear side metallization, wherein the soldering process comprises applying mechanical pressure to the front side metallization.

Abstract: An image sensor device is disclosed, which blocks noise of a pad area. The image sensor device includes a substrate, a pad, and an impurity area. The substrate includes a first surface and a second surface, and includes first conductive impurities. The pad is disposed at the first surface of the substrate. The impurity area is formed in the substrate to overlap with the pad in a first direction, the impurity area being includes second conductive impurities different from the first conductive impurities.

Abstract: An actuator device has a temperature sensing means and a controller adapted to apply a high frequency AC signal to stimulate internal self-heating to thereby maintain a temperature of an actuator member of the device at a certain fixed temperature, this temperature being elevated with respect to an initial temperature of the actuator member. This ensures that thermal drift may be mitigated or eliminated by compensating for any changes in environmental temperature through raising or lowering the level of the heating signal.

Abstract: A display device includes a substrate that includes a display area and a peripheral area, a transistor in the display area, a pixel electrode connected to the transistor, a common electrode that overlaps the pixel electrode, and an organic insulation layer that is between the common electrode and the substrate, and overlaps at least a part of the peripheral area, wherein a thickness of a portion of the organic insulation layer overlapping the display area, and a thickness of a portion of the organic insulation layer overlapping the peripheral area, are different from each other, and the organic insulation layer includes a valley that penetrates the organic insulation layer, while overlapping the peripheral area.

Abstract: The present disclosure provide a method of preparing semiconductor device involving planarization processes. The method includes introducing dopants into the exposed portions of the substrate to form doped portions of the substrate; forming a crystalline overlayer on the doped portions of the substrate, wherein the crystalline overlayer has a conductivity lower than that of the doped portions of the substrate. The crystalline overlayer is formed by an epitaxial growth process, the crystalline overlayer is formed as a saddle shape, and the crystalline overlayer has an excess portion protruding from the substrate.

Abstract: A foldable, flexible display apparatus includes a flexible display panel which displays an image and includes a display side on which the image is displayed and of which portions thereof face each other in a folded state of the flexible display apparatus; a cover window on the display side of the flexible display panel and including: a window film comprising a transparent plastic film having a modulus of elasticity of about 6.3 gigapascals or more; and a coating layer on the window film, and configured to be transparent and to protect the window film from physical damage thereto; and an adhesive layer between the window film and the display side of the flexible display panel, and configured to have elasticity and bond the window film and the flexible display panel to each other.

Abstract: Disclosed herein are IC structures, packages, and devices that include planar III-N transistors with wrap-around gates and/or one or more wrap-around source/drain (S/D) contacts. An example IC structure includes a support structure (e.g., a substrate) and a planar III-N transistor. The transistor includes a channel stack of a III-N semiconductor material and a polarization material, provided over the support structure, a pair of S/D regions provided in the channel stack, and a gate stack of a gate dielectric material and a gate electrode material provided over a portion of the channel stack between the S/D regions, where the gate stack at least partially wraps around an upper portion of the channel stack.

Abstract: An image sensor and a method of manufacturing thereof are provided. The image sensor includes a substrate, a grid structure, and color filters. The substrate includes a pixel separation structure defining pixel regions, and a sub-pixel regions for each pixel region. The grid structure is disposed on the substrate and includes first fence segments provided between the sub-pixel regions, and second fence segments provided between neighboring pixel regions. The grid structure defines openings corresponding respectively to the sub-pixel regions. The color filters are disposed in the openings defined by the grid structure. Each of the color filters has a flat top surface and the flat top surface of each color filter is parallel to a bottom surface thereof.

Abstract: A photodiode array has buried photodiodes and vertical selection transistors. Trenches are lined with gate oxide and metallic plugs of first material lie within the trenches. Gate contacts of second material contact the metallic plugs, with photodiode diffusion regions adjacent the trenches as sources of vertical transistors, the metallic plugs form gates of the vertical transistors, and buried photodiode regions form sources of the vertical transistors. In embodiments, the first conductive material is tungsten, titanium nitride, titanium carbide, or aluminum and the second conductive material is polysilicon. The array is formed by trenching, growing gate oxide, and depositing first material in the trenches. The first material is etched to define metallic plugs, the second material is deposited onto the metallic plugs then masked and etched; and drain regions implanted. Etching the second material is performed by a reactive ion etch that stops upon reaching the metallic plugs.

Abstract: Gallium nitride-based monolithic microwave integrated circuits (MMICs) can comprise aluminum-based metals. Electrical contacts for gates, sources, and drains of transistors can include aluminum-containing metallic materials. Additionally, connectors, inductors, and interconnect devices can also comprise aluminum-based metals. The gallium-based MMICs can be manufactured in complementary metal oxide semiconductor (CMOS) facilities with equipment that produces silicon-based semiconductor devices.