Patents Examined by Scott B. Geyer
  • Patent number: 10553639
    Abstract: A solid-state imaging device includes: a first electrode formed above a semiconductor substrate; a photoelectric conversion film formed on the first electrode and for converting light into signal charges; a second electrode formed on the photoelectric conversion film; a charge accumulation region electrically connected to the first electrode and for accumulating the signal charges converted from the light by the photoelectric conversion film; a reset gate electrode for resetting the charge accumulation region; an amplification transistor for amplifying the signal charges accumulated in the charge accumulation region; and a contact plug in direct contact with the charge accumulation region, comprising a semiconductor material, and for electrically connecting to each other the first electrode and the charge accumulation region.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: February 4, 2020
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Yusuke Sakata, Mitsuyoshi Mori, Yutaka Hirose, Hiroshi Masuda, Hitoshi Kuriyama, Ryohei Miyagawa
  • Patent number: 10547024
    Abstract: A display device is provided. The display device includes a display panel including first and second display substrates that face each other, having an overlap area in which the first and second display substrates overlap with each other, and having a protruding area on one side of the overlap area, a sealing member between the first and second display substrates along edges of the overlap area, and at least one chamfered portion including a first chamfered portion, which is formed on at least one side of the protruding area, and a second chamfered portion, which is formed on the overlap area and adjacent to the first chamfered portion, wherein in the second chamfered portion, an end of the first display substrate is positioned beyond an end of the second display substrate.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: January 28, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hyun Min Hwang, Yong Kyu Jang, Jae Kyung Go, Dong Jo Kim, Young Min Kim, Chan Young Park, Dong Won Han
  • Patent number: 10541192
    Abstract: Microfeature workpieces having alloyed conductive structures, and associated methods are disclosed. A method in accordance with one embodiment includes applying a volume of material to a bond pad of a microfeature workpiece, with the volume of material including a first metallic constituent and the bond pad including a second constituent. The method can further include elevating a temperature of the volume of material while the volume of material is applied to the bond pad to alloy the first metallic constituent and the second metallic constituent so that the first metallic constituent is alloyed generally throughout the volume of material. A thickness of the bond pad can be reduced from an initial thickness T1 to a reduced thickness T2.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: January 21, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Rick C. Lake, William M. Hiatt
  • Patent number: 10541190
    Abstract: An apparatus is described that includes a first semiconductor die. A second semiconductor die is stacked on the first semiconductor die. The first semiconductor die has a larger surface area than the second semiconductor die such that there exists a peripheral region of the first semiconductor die that is not covered by the second semiconductor die. The apparatus includes thermally conductive material above the second semiconductor die. The apparatus includes a compound mold between the thermally conductive material and both the second semiconductor die and the peripheral region of the first semiconductor die. The apparatus includes a thermally conductive structure extending through the compound mold that thermally couples the peripheral region to the thermally conductive material.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: January 21, 2020
    Assignee: Intel Corporation
    Inventors: Chandra Jha, Eric Li
  • Patent number: 10530038
    Abstract: A semiconductor package device includes a substrate, an antenna and a conductor. The substrate has an upper surface. The antenna is disposed on the upper surface of the substrate. The conductor is disposed on the upper surface of the substrate and surrounds the antenna. The conductor has a first surface facing toward the antenna and a second surface opposite to the first surface. The second surface of the conductor is spaced apart from the upper surface of the substrate.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: January 7, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Shao-En Hsu, Huei-Shyong Cho, Shih-Wen Lu
  • Patent number: 10529500
    Abstract: The present invention provides a method (201) for making composite materials used in making flexible supercapacitor prototype (106). The method (201) comprises the steps of rolling the exfoliated graphite (101) using rolling instrument (103) to form an EG sheet (104). In-situ coating is done on EG sheet (104) to form flexible EG or polymer electrode which is used to make supercapacitors (106). A graphite powder (101) is added with the mixture of HNO3 and H2SO4 in the ratio of 1:3 resulting in oxidized graphite. Oxidized graphite undergoes thermal shock in an isothermal furnace at a temperature of 900 degree Celsius for time duration of 2 minutes resulting in EG worms (102). These EG worms are rolled using a rolling instrument (103) to form an EG sheet (104).
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: January 7, 2020
    Inventor: Venkataramana Gedela
  • Patent number: 10529826
    Abstract: A method includes forming an active layer, forming a gate structure above a channel region of the active layer, forming a sidewall spacer adjacent the gate structure, forming a first dielectric layer adjacent the sidewall spacer, recessing the gate structure to define a gate cavity, forming an inner spacer in the gate cavity, forming a cap layer in the gate cavity, recessing the first dielectric layer and the sidewall spacer to expose sidewall surfaces of the cap layer, removing the inner spacer to define a first spacer cavity, forming an upper spacer in the spacer cavity and contacting sidewall surfaces of the cap layer, forming a second dielectric layer above the upper spacer and the cap layer, and forming a first contact structure at least partially embedded in the second dielectric layer and contacting a surface of the upper spacer.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: January 7, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Julien Frougier, Ruilong Xie, Chanro Park, Kangguo Cheng
  • Patent number: 10522397
    Abstract: A miniaturized transistor is provided. A first layer is formed over a third insulator over a semiconductor; a second layer is formed over the first layer; an etching mask is formed over the second layer; the second layer is etched using the etching mask until the first layer is exposed to form a third layer; a selective growth layer is formed on a top surface and a side surface of the third layer; the first layer is etched using the third layer and the selective growth layer until the third insulator is exposed to form a fourth layer; and the third insulator is etched using the third layer, the selective growth layer, and the fourth layer until the semiconductor is exposed to form a first insulator.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: December 31, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuta Endo, Hideomi Suzawa, Sachiaki Tezuka, Tetsuhiro Tanaka, Toshiya Endo, Mitsuhiro Ichijo
  • Patent number: 10522438
    Abstract: A package structure includes a redistribution layer, a chip, an encapsulant, a plurality of under ball release layers, and a plurality of solder balls. The redistribution layer includes a first surface, a second surface opposite to the first surface, and a patterned circuit layer, wherein the patterned circuit layer includes a plurality of pads protruding from the first surface. The chip is disposed on the second surface and electrically connected to the patterned circuit layer. The encapsulant is disposed on the second surface and encapsulates the chip. The under ball release layers cover the pads respectively. The solder balls are disposed on the under ball release layers and electrically connected to the pads.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: December 31, 2019
    Assignee: Industrial Technology Research Institute
    Inventors: Chun-Yi Cheng, Wei-Yuan Cheng, Shu-Wei Kuo, Yu-Jhen Yang
  • Patent number: 10522561
    Abstract: Embodiments of a method for forming a three-dimensional (3D) memory devices are disclosed. The method can comprise forming a device wafer including: forming a first channel hole penetrating a first alternating layer stack of a device wafer, forming an epitaxial layer on a bottom of the first channel hole, and forming a first channel layer on a sidewall of the first channel hole. The method can further comprise forming at least one connecting wafer, each connecting wafer including a second channel hole penetrating a second alternating layer stack without an epitaxial layer on a bottom of the second channel hole; and bonding the at least one connecting wafer and the device wafer, such that a second channel layer on a sidewall of the second channel hole in each connecting wafer is electrically connected with the first channel layer in the device wafer.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: December 31, 2019
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Kun Zhang, Fandong Liu, Zhiliang Xia
  • Patent number: 10522599
    Abstract: A foldable, flexible display apparatus includes a flexible display panel which displays an image and includes a display side on which the image is displayed and of which portions thereof face each other in a folded state of the flexible display apparatus; a cover window on the display side of the flexible display panel and including: a window film comprising a transparent plastic film having a modulus of elasticity of about 6.3 gigapascals or more; and a coating layer on the window film, and configured to be transparent and to protect the window film from physical damage thereto; and an adhesive layer between the window film and the display side of the flexible display panel, and configured to have elasticity and bond the window film and the flexible display panel to each other.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: December 31, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yong-Cheol Jeong, Seung-Wook Nam, So-Yeon Han, Kyu-Young Kim, Ah-Young Kim, Gui-Nam Min, Kyu-Taek Lee
  • Patent number: 10504899
    Abstract: A semiconductor device includes a first circuit and a second circuit. The first circuit includes a first gate, a first drain, and a first source. The second circuit includes a second gate, a second drain, and a second source. The first drain and the first source of the first circuit include a first doping material with a first concentration. A gate pitch and a gate critical dimension of the first gate of the first circuit are the same as a gate pitch and a gate critical dimension of the second gate of the second circuit. The second drain and the second source of the second circuit include a second doping material with a second concentration, wherein the first concentration is different from the second concentration.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: December 10, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon-Jhy Liaw
  • Patent number: 10505084
    Abstract: The present invention provides a micro light-emitting-diode display panel and a manufacturing method thereof. The micro light-emitting-diode display panel which presses and fixes the micro light-emitting-diodes into a resin adhesive layer by filling the resin adhesive layer in the pixel groove. Meanwhile, the electrode at the bottom of the micro light-emitting-diode is guided to the top of the micro light-emitting-diode by the connection electrode, making the two electrodes of the micro light-emitting-diode are at the top, to facilitate the connection between the electrodes of the micro light-emitting-diode and the electrode points.
    Type: Grant
    Filed: February 18, 2019
    Date of Patent: December 10, 2019
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Macai Lu
  • Patent number: 10504922
    Abstract: This disclosure provides an array substrate, a display panel and a display device. The array substrate comprises a substrate, a transistor and a photosensitive element above the substrate. The transistor comprises a gate and is used for controlling display of pixels. The photosensitive element comprises a light-transmissive electrode and a photosensitive layer, the light-transmissive electrode being used for allowing sensitive light rays reflected by a surface of a fingerprint pressed thereon to pass through and impinge on the photosensitive layer, and the light-transmissive electrode being connected to the gate. By connecting the light-transmissive electrode to the gate, the array substrate achieves synchronization of image display and fingerprint identification without individually providing a scan function for fingerprint identification, which greatly facilitates the actual applications requiring synchronization of image display and fingerprint identification.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: December 10, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Yingming Liu, Xue Dong, Haisheng Wang, Xiaochuan Chen, Xiaoliang Ding, Shengji Yang, Weijie Zhao, Changfeng Li, Lei Wang, Pengpeng Wang, Wei Liu
  • Patent number: 10504906
    Abstract: A method of forming a finFET SRAM and related device, are provided. Embodiments include forming a plurality of silicon fins in a substrate; and forming a gate over each of the fins, wherein all of the fins are diagonally skewed in a single direction relative to the gates, and all of the gates extend in a single direction relative to the respective fins.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: December 10, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ming-Cheng Chang, Nigel Chan, Ralf Van Bentum
  • Patent number: 10497791
    Abstract: The present disclosure relates to the technical field of semiconductors, and discloses a semiconductor device and a manufacturing method therefor. The manufacturing method includes: providing a semiconductor structure, where the semiconductor structure includes an active region and a gate structure located in the active region, the gate structure at least including a gate electrode, and the active region exposing an upper surface of the gate electrode; forming a surface insulator layer on the upper surface of the gate electrode; forming a patterned interlayer dielectric layer on the semiconductor structure, where the interlayer dielectric layer covers the surface insulator layer, and has a first through hole exposing a portion of the active region; and forming a conductive contact layer passing through the first through hole and contacting with the active region.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: December 3, 2019
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Xianming Zhang, Ling Tang, Leibin Yuan, Feng Dou, Feng Chen
  • Patent number: 10490600
    Abstract: Various embodiments of a modular unit for a topologic qubit and of scalable quantum computing architectures using such modular units are disclosed herein. For example, one example embodiment is a modular unit for a topological qubit comprising 6 Majorana zero modes (MZMs) on a mesoscopic superconducting island. These units can provide the computational MZMs with protection from quasiparticle poisoning. Several possible realizations of these modular units are described herein. Also disclosed herein are example designs for scalable quantum computing architectures comprising the modular units together with gates and reference arms (e.g., quantum dots, Majorana wires, etc.) configured to enable joint parity measurements to be performed for various combinations of two or four MZMs associated with one or two modular units, as well as other operations on the states of MZMs.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: November 26, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Michael Freedman, Chetan Nayak, Roman Lutchyn, Torsten Karzig, Parsa Bonderson
  • Patent number: 10490473
    Abstract: A chip package module includes an encapsulation layer, a chip, a substrate and a plurality of blind-hole electrodes. The encapsulation layer includes a first surface and a second surface opposite to the first surface. The chip includes a third surface and a fourth surface opposite to the third surface. A metal bump is fabricated on the third surface of the chip. The chip is embedded into the encapsulation layer from the first surface of the encapsulation layer. The metal bump is exposed from the first surface of the encapsulation layer. The substrate includes a metal layer, wherein the metal layer of the substrate is bonded to the chip through the metal bump. The plurality of blind-hole electrodes pass through the second surface of the encapsulation layer and are electrically connected to the metal layer of the substrate.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: November 26, 2019
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Shin-Yi Huang, Yu-Min Lin, Tao-Chih Chang
  • Patent number: 10490645
    Abstract: Some embodiments include semiconductor devices having first transistors of a first channel type and having second transistors of a second channel type. The first transistors include a first gate electrode, a first nitrogen-doped gate dielectric layer and a first high-k material. The second transistors include a second gate electrode, a second nitrogen-doped gate dielectric layer and a second high-k material. The second nitrogen-doped gate dielectric layer is doped with nitrogen to a different peak concentration than the first nitrogen-doped gate dielectric layer. Some embodiments include methods of forming PMOS and NMOS transistors having nitrogen-doped gate dielectric material.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: November 26, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Yoshikazu Moriwaki
  • Patent number: 10483243
    Abstract: A semiconductor device includes a chip stack structure including a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first semiconductor chip includes a first substrate, a first circuit layer on a front surface of the first substrate, and a first connecting layer disposed on the first circuit layer and including a first metal pad electrically connected to the first circuit layer. The second semiconductor chip includes a second substrate, a second circuit layer on a front surface of the second substrate, and a second connecting layer disposed on the second circuit layer and including a second metal pad electrically connected to the second circuit layer. The first connecting layer faces the second connecting layer. The first and second metal pads are in contact with each other to couple the first and second semiconductor chips to each other.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: November 19, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Donghyun Kim, DooWon Kwon