Abstract: A semiconductor device includes a semiconductor body comprising a first surface and an edge surface, a contact electrode formed on the first surface and comprising an outer edge side, and a passivation layer section conformally covering the outer edge side of the contact electrode. The passivation layer section is a multi-layer stack comprising a first layer, a second layer, and a third layer. Each of the first, second and third layers include outer edge sides facing the edge surface and opposite facing inner edge sides. The outer edge side of the contact electrode is disposed laterally between the inner edge sides and the outer edge sides of each layer.

Abstract: A semiconductor device has a first substrate and a second substrate. An opening is formed through the second substrate. A first semiconductor component and second semiconductor component are disposed between the first substrate and second substrate. The second substrate is electrically coupled to the first substrate through the first semiconductor component. A first terminal of the first semiconductor component is electrically coupled to the first substrate. A second terminal of the first semiconductor component is electrically coupled to the second substrate. The second semiconductor component extends into the opening. An encapsulant is deposited over the first substrate and second substrate.

Abstract: A power semiconductor device includes a substrate and a semiconductor element bonded onto a first surface of the substrate through use of a sintered metal bonding material. The substrate has a plurality of dimples formed in the first surface and located outside a location immediately below a heat generation unit of the semiconductor element. The sintered metal bonding material is supplied onto the substrate after the formation of the dimples, and the semiconductor element is bonded to the substrate through application of heat and a pressure thereto.

Abstract: In one embodiment, a semiconductor device includes a first substrate including first and second regions on its surface, a first control circuit on the first substrate in the first region, a first memory cell array above the first control circuit in the first region and connected to the first control circuit, and a first pad above the first memory cell array in the first region and connected to the first control circuit. The device further includes a second control circuit on the first substrate in the second region, a second memory cell array above the second control circuit in the second region and connected to the second control circuit, a second pad above the second memory cell array in the second region and connected to the second control circuit, and a connection line above the first and second memory cell arrays and connecting the first and second pads.

Abstract: Disclosed herein are a radiation detector and a method of making it. The radiation detector is configured to absorb radiation particles incident on a semiconductor single crystal of the radiation detector and to generate charge carriers. The semiconductor single crystal may be a CdZnTe single crystal or a CdTe single crystal. The method may comprise forming a recess into a substrate of semiconductor; forming a semiconductor single crystal in the recess; and forming a heavily doped semiconductor region in the substrate. The semiconductor single crystal has a different composition from the substrate. The heavily doped region is in electrical contact with the semiconductor single crystal and embedded in a portion of intrinsic semiconductor of the substrate.

Abstract: A photovoltaic cell includes a germanium-containing well embedded in a single crystalline silicon substrate and extending to a proximal horizontal surface of the single crystalline silicon substrate, wherein germanium-containing well includes germanium at an atomic percentage greater than 50%. A silicon-containing capping structure is located on a top surface of the germanium-containing well and includes silicon at an atomic percentage greater than 42%. The silicon-containing capping structure prevents oxidation of the germanium-containing well. A photovoltaic junction may be formed within, or across, the trench by implanting dopants of a first conductivity type and dopants of a second conductivity type.

Abstract: Provided are a solid-state imaging device, a manufacturing method thereof, and an electronic device. The solid-state imaging device includes a first semiconductor layer in which a first photoelectric conversion unit and a first floating diffusion are formed, a second semiconductor layer in which a second photoelectric conversion unit and a second floating diffusion are formed, and a wiring layer including a wiring electrically connected to the first and second floating diffusions. The first semiconductor layer and the second semiconductor layer are laminated, and the wiring layer is formed on a side of the first or second semiconductor layer, the side being opposite to a side on which the first semiconductor layer and the second semiconductor layer face each other.

Abstract: A package structure includes an insulating encapsulation, at least one die, and conductive structures. The at least one die is encapsulated in the insulating encapsulation. The conductive structures are located aside of the at least one die and surrounded by the insulating encapsulation, and at least one of the conductive structures is electrically connected to the at least one die. Each of the conductive structures has a first surface, a second surface opposite to the first surface and a slant sidewall connecting the first surface and the second surface, and each of the conductive structures has a top diameter greater than a bottom diameter thereof, and wherein each of the conductive structures has a plurality of pores distributed therein.

Abstract: A superconducting circuit includes a first component having a first connection point. The first connection point has a first width. The superconducting circuit includes a second component having a second connection point. The second connection point has a second width that is larger than the first width. The superconducting circuit includes a superconducting connector shaped to reduce current crowding. The superconducting connector electrically connects the first connection point and the second connection point. The superconducting connector includes a first taper positioned adjacent the first connection point and having a non-linear shape and a second taper positioned adjacent the second connection point.

Abstract: A semiconductor device is provided. The semiconductor device includes a base substrate; and a first gate structure and doped source/drain layers on the base substrate. The doped source/drain layers are on both sides of the first gate structure. The semiconductor device further includes a dielectric layer on a surface of the base substrate. The dielectric layer covers the doped source/drain layers, and the dielectric layer contains a first trench on the doped source/drain layer. The first trench includes a first region filled by an insulation layer and a second region filled by first conductive structure under the insulation layer. A top size of the insulation layer in the first region is larger than a bottom size of the insulation layer in the first region. A maximum size of the first conductive structure in the second region is smaller than the bottom size of the insulation layer in the first region.

Abstract: A pixel-array substrate includes (i) a semiconductor substrate including a photodiode region and a floating diffusion region, and (ii) a vertical-transfer-gate structure that includes a trench and a gate electrode. The trench is defined by a bottom surface and a sidewall surface of the substrate each located between a front substrate-surface and a back substrate-surface thereof. The trench extends into the substrate. In a cross-sectional plane perpendicular to the front substrate-surface and intersecting the floating diffusion region, the photodiode region, and the sidewall surface, (a) the trench is located between the floating diffusion region and the photodiode region, and (b) a top section of the sidewall surface is adjacent to the floating diffusion region. A gate electrode partially fills the trench such that the top section and a conductive-surface of the gate electrode in-part define a recess located between the floating diffusion region and the gate electrode.

Abstract: A sensor for performing measurements is disclosed. It comprises: a substrate; a plurality of graphene field-effect transistors (GFET) deposited on a central area of the substrate; at least one source electrode connected to the GFETs through at least one first metal track, wherein the at least one source electrode is disposed at the periphery of the substrate; at least one drain electrode connected to the GFETs through at least one second metal track, wherein the at least one drain electrode is disposed at the periphery of the substrate; and at least one gate electrode, disposed at least in part at the center of the substrate, wherein, in use of the sensor, when a sample is deposited in contact with the gate electrode and the GFETs, the sample allows gating between the gate electrode and the GFETs.

Abstract: A light emitting device including a first LED sub-unit, a second LED sub-unit disposed under the first LED sub-unit, a third LED sub-unit disposed under the second LED sub-unit, a first ohmic electrode interposed between the first LED sub-unit and the second LED sub-unit, and in ohmic contact with the first LED sub-unit, a second ohmic electrode interposed between the second LED sub-unit and the third LED sub-unit, and in ohmic contact with the second LED sub-unit, a third ohmic electrode interposed between the second ohmic electrode and the third LED sub-unit, and in ohmic contact the third LED sub-unit, a plurality of electrode pads disposed on the first LED sub-unit, in which at least one of the first ohmic electrode, the second ohmic electrode, and the third ohmic electrode has a patterned structure.

Abstract: A light emitting device including a substrate, a light emitting structure disposed on the substrate and having a first light emitting region, a second light emitting region, and a third light emitting region, and an insulation layer to block unintended electrical connection between the first light emitting region and the second light emitting region, or between the second light emitting region and the third light emitting region, in which each of the first light emitting region, the second light emitting region, and the third light emitting region comprises a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer, and a center of the first light emitting region overlaps a center of the second light emitting region and a center of the third light emitting region.

Abstract: Described herein are techniques to reduce or remove the impact of secondary path photons and/or charge carriers on storage bins of an integrated device to improve noise performance, and thus, sample analysis. Some embodiments relate to optical rejection techniques such as including an optical barrier positioned to block at least some photons from reaching the storage bins. Some embodiments relate to electrical rejection techniques such as including an electrical barrier configured to block at least some charge carriers from reaching the storage bins along at least one secondary path. Some embodiments relate to an integrated device in which at least one storage bin is shaped and/or positioned relative to the photodetector to facilitate receipt of some charge carriers (e.g., fluorescent emission charge carriers) and/or photons and to impede receipt of other charge carriers (e.g., noise charge carriers) and/or photons.

Abstract: According to an embodiment, a semiconductor memory device comprises: a stacked body that includes a plurality of control gate electrodes stacked above a substrate; a memory columnar body that extends in a first direction above the substrate and configures a memory string along with the stacked body; and a source contact that extends in the first direction and is electrically connected to one end of the memory string. Moreover, this source contact is adjacent to the stacked body via a spacer insulating layer. Furthermore, a spacer protective layer including a nitride or a metal oxide is provided between these source contact and spacer insulating layer.

Abstract: A method of producing a crystalline silicon film includes forming a first silicon film that is amorphous at formation, forming a doped film of silicon or germanium on the first silicon film, the doped film being amorphous at formation; and annealing the structure to crystallize the doped film and the first silicon film. A method of producing a crystalline silicon film includes forming a Six1Ge1-x1 film on a substrate, forming a Six2Ge1-x2 film on the Six1Ge1-x1 film, the Six1Ge1-x1 film being amorphous at formation and having a first thermal budget for crystallization, the Six2Ge1-x2 film being amorphous at formation and having a second thermal budget for crystallization, the second thermal budget being lower than the first thermal budget, forming a silicon film on the Six2Ge1-x2 film, the silicon film being amorphous at formation; and annealing to crystallize the Six1Ge1-x1 film, the Six2Ge1-x2 film, and the silicon film.

Abstract: In some examples, an electronic device comprises a first component having a surface, a second component having a surface, and a bond layer positioned between the surfaces of the first and second components to couple the first and second components to each other. The bond layer includes a set of metallic nanowires and a dielectric portion. The dielectric portion comprises a polymer matrix and dielectric nanoparticles.

Abstract: A method of forming a microphone device includes: forming a through-hole in a substrate wafer; providing a second wafer; bonding the second wafer to the substrate wafer; and forming a top electrode over a first surface of a single-crystal piezoelectric film of the second wafer. The second wafer may include the single-crystal piezoelectric film. The single-crystal piezoelectric film may have a first surface and an opposing second surface. The second wafer may further include a bottom electrode arranged adjacent to the second surface, and a support member over the single-crystal piezoelectric film. The through-hole in substrate wafer may be at least substantially aligned with at least one of the top electrode and the bottom electrode.

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a substrate comprising sidewalls that define a trench. A capacitor comprising a plurality of conductive layers and a plurality of dielectric layers that define a trench segment is disposed within the trench. A width of the trench segment continuously increases from a front-side surface of the substrate in a direction towards a bottom surface of the trench.