Abstract: An interrupt request generating process can include determining a first interrupt triggering event has occurred after a predetermined period of time in which no interrupt triggering event occurred. In response to determining that the first interrupt triggering event has occurred, the interrupt request generating process may generate a first interrupt request without adding an intentional delay, and initiating a timer configured to expire after a predetermined time interval. When a second interrupt triggering event is determined to have occurred before the timer expires, a second interrupt request is delayed from being generated until the timer expires.

Abstract: A circuit device includes first and second physical layer circuits, a bus switch circuit that switches connection between a first bus and a second bus, which are compliant with the USB standard, ON in a first period and OFF in a second period, and a processing circuit that performs processing for transferring a packet in a transfer route constituted by the first bus, the first and second physical layer circuits, and the second bus, in the second period. The second physical layer circuit includes a disconnection detection circuit that detects device disconnection of a device connected to the second bus side. If device disconnection is detected in the second period, the connection between the first bus and the second bus is switched from off to on after a wait period has elapsed from the timing at which the device disconnection was detected.

Abstract: An information handling system includes a processor complex with a root complex that provides N serial data lanes, where N is an integer. The information handling system also includes boot process logic that determines that a device is coupled to X of the serial data lanes, where X is an integer less than N, determines that no device is coupled to Y of the serial data lanes, where Y is an integer less than or equal to N?X, and allocates a portion of bus resources of the root complex to the device, the portion being greater (X+Y)/N.

Abstract: An electronic meeting tool for communicating arbitrary media content from users at a meeting includes a node configuration operating a display node of a communications network that is coupled to a display. The node configuration receives user selected arbitrary media content and controls display of the user selected arbitrary media content on the display. At least one peripheral device communicates the user selected arbitrary media content via the communications network. The peripheral device is a connection unit including a connector that couples to a port of a processing device having a second display, a memory and an operating system; and a transmitter communicating with the communications network. A program is provided to run on the operating system of the processing device and obtains user selected arbitrary media content, while leaving a zero footprint on termination.

Abstract: A system and method for performing copy offload operations. When a copy offload operation from a first volume (pointing to a first medium) to a second volume (pointing to a second medium) is requested, the copy offload operation is performed without accessing the data being copied. A third medium is created, and the first medium is recorded as the underlying medium of the third medium. The first volume is re-pointed to the third medium. Also, a fourth medium is created, the second volume is re-pointed to the fourth medium, and the second medium is recorded as the underlying medium of the targeted range of the fourth medium. All other ranges of the fourth medium have the second medium as their underlying medium.

Abstract: An example data processing engine (DPE) for a DPE array in an integrated circuit (IC) includes a core, a memory including a data memory and a program memory, the program memory coupled to the core, the data memory coupled to the core and including at least one connection to a respective at least one additional core external to the DPE; support circuitry including hardware synchronization circuitry and direct memory access (DMA) circuitry each coupled to the data memory, and a stall circuit coupled to the core configured to stall or resume the core in response to one or more inputs.

Abstract: Embodiments of the present invention are directed to a configuration interface of a network ASIC. The configuration interface allows for two modes of traversal of nodes. The nodes form one or more chains. Each chain is in a ring or a list topology. A master receives external access transactions. Once received by the master, an external access transaction traverses the chains to reach a target node. A target node either is an access to a memory space or is a module. A chain can include at least one decoder. A decoder includes logic that determines which of its leaves to send an external access transaction to. In contrast, if a module is not the target node, then the module passes an external access transaction to the next node coupled thereto; otherwise, if the module is the target node, the transmission of the external access transaction stops at the module.

Abstract: A detection control device including a USB connection port, a first detection circuit, a second detection circuit, a control circuit, a first switching circuit and a second switching circuit is provided. When a first pin group of the USB connection port is coupled to an external device, the first detection circuit generates a first detection signal according to a first time constant. When a second pin group of the USB connection port is coupled to the external device, the second detection circuit generates a second detection signal according to a second time constant. The control circuit generates a first control signal and a second control signal according to the first and second detection signals. Each of the first and second switching circuits communicates with the external device via the first or second pin groups according to either the first control signal or the second control signal.

Abstract: The invention provides an improved electronic device docking apparatus which is more convenient for the user and ergonomically placed about a monitor close to the standard viewing range of a user's workspace. The inventive device includes a ledge for accepting an electronic device and one or more features for mounting the improved electronic device docking apparatus to a monitor.

Abstract: When executed, a transaction-hint instruction specifies a transaction-count-to-completion (CTC) value for a transaction. The CTC value indicates how far a transaction is from completion. The CTC may be a number of instructions to completion or an amount of time to completion. The CTC value is adjusted as the transaction progresses. When a disruptive event associated with inducing transactional aborts, such as an interrupt or a conflicting memory access, is identified while processing the transaction, processing of the disruptive event is deferred if the adjusted CTC value satisfies deferral criteria. If the adjusted CTC value does not satisfy deferral criteria, the transaction is aborted and the disruptive event is processed.

Abstract: The present invention enables an unaligned access of a DMA controller to be dealt at the time of obtaining trace data. A DMA controller receives a DMA request and accesses a memory via a bus on a predetermined access unit basis in accordance with the received DMA request. When the DMA request indicates “read”, a trace interface outputs the data obtained from the memory by the DMA controller, a start address designated by the DMA request, and valid transfer size in the data obtained from the memory to a trace circuit. The trace circuit stores data of the amount of the valid transfer size from the start address designated by the DMA request in the data obtained from the memory into the trace buffer.

Abstract: An electronic device according to various embodiments may include a housing including a first surface facing a first direction and a second surface facing a second direction opposite the first direction, a touchscreen display exposed through a portion of the first surface, at least one wireless and/or wired communication circuit disposed inside the housing, at least one processor disposed inside the housing and electrically connected to the display and the communication circuit, and a memory disposed inside the housing and electrically connected to the processor. The communication circuit and/or the at least one processor may be configured to be in one of a plurality of states for exchanging data on a bus based on a plurality of generations of the peripheral component interconnect express (PCIe) standard.

Abstract: A data processing method for a data processing system, comprising: initializing a value of a counter associated with a first entry to indicate a number of destinations of other entries on which the first entry depends; changing the value of the counter in a first direction in response to selecting a first one of the other entries; and changing the value of the counter in a second direction opposite the first direction in response to cancelling a second one of the other entries.

Abstract: A device and method for providing performance information about a processing device. A stream of performance data is generated by one or more devices whose performance is reflected in the performance data. This performance data stream is then provided to a parallel port for outputting thereof.

Abstract: This application relates to transfer of digital audio data between a host device (200) and an accessory apparatus (101) that may be connected to the host device via a suitable connector (106), such as a USB connector. A path selector (240, 270) is operable to establish either a first digital data path (201) or a second digital data path (202) for transfer of digital data. The first digital data path (201) includes a first data bus host (103) and a general purpose digital data interface (131) suitable for bulk data transfer between the first data bus host and the applications processor (110) of the device. This may be a default USB path. The second digital data path (202) includes a second data bus host (230) and at least one pair of second path data interfaces (140, 141). The second data bus host (230) does not form part of the applications processor and each of said second path data interfaces comprises a digital audio interface suitable for streaming of audio data.

Abstract: An apparatus is described having an instruction execution pipeline that has a vector functional unit to support a vector multiply add instruction. The vector multiply add instruction to multiply respective K bit elements of two vectors and accumulate a portion of each of their respective products with another respective input operand in an X bit accumulator, where X is greater than K.

Abstract: A method for operating a bus system of an automation system, wherein the bus system has an Ethernet-based network and a coupler and a local bus and a local bus user. An Ethernet telegram is received via the Ethernet-based network at the coupler, wherein the Ethernet telegram has an identifier associated with a fieldbus protocol wherein the Ethernet telegram has process data, conforming to the fieldbus protocol, for the local bus user. The process data is acquired and the identifier from the Ethernet telegram by the coupler. A local bus telegram is generated by the coupler, wherein the local bus telegram has a local-bus-specific local bus header and a local bus payload section. The process data is inserted, together with the identifier, into the local bus telegram by the coupler. The local bus telegram is transmitted from the coupler to the local bus user.

Abstract: A drive circuit for a serial communications system is provided. The drive circuit may include a mode controller, a pre-drive circuit, and a main drive circuit. The main drive circuit includes multiple mode control switches and at least one pair of differential switches. The mode controller is configured to: generate a mode control signal, and transmit the mode control signal to the main drive circuit. The pre-drive circuit is configured to: convert a differential digital signal into a differential control signal, and transmit the differential control signal to the main drive circuit. The main drive circuit controls on/off states of the multiple mode control switches according to the mode control signal, and works in corresponding working modes. The drive circuit controls the states of the mode control switches in the main drive circuit, so that the main drive circuit works in different working modes.

Abstract: In an embodiment, processors may have associated special purpose registers (SPRs) such as model specific registers (MSRs), used to communicate IPIs between the processors. In an embodiment, several types of IPIs may be defined, such as one or more of an immediate type, a deferred type, a retract type, and/or a non-waking type. The immediate IPI may be delivered and may cause the target processor to interrupt in response to receipt of the IPI. The deferred IPI may be delivered within a defined time limit, and not necessarily on receipt by the target processor. The retract IPI may cause a previously transmitted IPI to be cancelled (if it has not already caused the target processor to interrupt). A non-waking IPI may not cause the target processor to wake if it is asleep, but may be delivered when the target processor is awakened for another reason.

Abstract: A virtualization platform for Network Functions Virtualization (NFV) is provided. The virtualization platform may include a host processor coupled to an acceleration coprocessor. The acceleration coprocessor may be a reconfigurable integrated circuit to help provide improved flexibility and agility for the NFV. The coprocessor may include multiple virtual function hardware acceleration modules each of which is configured to perform a respective accelerator function. A virtual machine running on the host processor may wish to perform multiple accelerator functions in succession at the coprocessor on a given data. In one suitable arrangement, intermediate data output by each of the accelerator functions may be fed back to the host processor. In another suitable arrangement, the successive function calls may be chained together so that only the final resulting data is fed back to the host processor.