Abstract: A data processing system comprises a master node to initiate data transmissions; one or more slave nodes to receive the data transmissions; and a home node to control coherency amongst data stored by the data processing system; in which at least one data transmission from the master node to one of the one or more slave nodes bypasses the home node.

Abstract: Provided are a device and computer readable storage medium for programming a memory module to initiate a training mode in which the memory module transmits continuous bit patterns on a side band lane of the bus interface; receiving the bit patterns over the bus interface; determining from the received bit patterns a transition of values in the bit pattern to determine a data eye between the determined transitions of the values; and determining a setting to control a phase interpolator to generate interpolated signals used to sample data within the determined data eye.

Abstract: A server system and a data access method using the same are provided. The server system includes a first server and a second server. The first server includes a first host, a first expander unit and a first peripheral device. The first expander unit is coupled to the first host, and the first peripheral device is coupled to the first expander unit. The second server includes a second host, a second expander unit and a second peripheral device. The second expander unit is coupled to the second host, and the second peripheral device is coupled to the second expander unit. The first expander unit is connected to the second expander unit. The first host accesses the first peripheral device through the first expander unit. The first host further accesses the second peripheral device through the first expander unit and the second expander unit while the second host malfunctions.

Abstract: A slave device for a serial synchronous full duplex bus system, which has a data input stage, a clock input stage, an interface logic, a synchronization delay flip-flop, and a data output stage. The slave device is manufactured using nanometer technologies. Also, a method for operating the slave device.

Abstract: Described is an apparatus for converting binary data to ternary and back such that the apparatus comprises: a first look-up table (LUT) having a mapping of 19 binary bits to 12 ternary trits; and a first logic to receive a binary input and to convert the binary input to a ternary output according to the first LUT.

Abstract: In accordance with embodiments of the present disclosure, an information handling system may include a processor and a port configured to couple a hot-pluggable device received in the information handling system to the processor. The port may comprise a hot-plug controller configured to detect the insertion of the hot-pluggable device into the information handling system and delay communication of a hot-plug interrupt to an operating system executing on the processor in response to the insertion of the hot-pluggable device in order to allow for platform-specific configuration of the hot-pluggable device.

Abstract: An HDMI apparatus and a method for controlling the same are provided. The HDMI apparatus includes an HDMI connection port, a control circuit, a master circuit, a slave circuit, and a switch circuit. The master circuit and the slave circuit are respectively configured to generate a master HDMI output signal and a slave HDMI output signal. The switch circuit is selectively conducted in a first conductive state and a second conductive state according to a control signal generated by the control circuit. In the first conductive state, the switch circuit is electrically connected to the master circuit, so that the master HDMI output signal is output through the HDMI connection port. In the second conductive state, the switch circuit is electrically connected to the slave circuit, so that the slave HDMI output signal is output through the HDMI connection port.

Abstract: Storage arrays, systems and methods for processing commands to enable SCSI-level forwarding between an active controller and a standby controller are provided. In one example, the standby controller has ports that operate in an asymmetric logical unit access (ALUA) standby (SB) mode. One such method includes receiving a command by a port of the standby controller, wherein the port operates in the ALUA SB mode. The method includes identifying that the command is of a type that is predefined for forwarding, and forwarding the command from a SCSI layer of the standby controller to a SCSI layer of the active controller. The method further includes processing the command in a user space of the active controller to generate return data and forwarding the return data from the active controller to the standby controller. The method additionally includes sending the return data to the initiator, over the port of the standby controller.

Abstract: A memory system and an operating method thereof include: at least a CPU including multiple CPU cores, wherein the multiple CPU cores include reserved CPU cores and host CPU cores; at least a PCIe link coupled with the CPU, wherein the PCIe link includes at least a PCIe switch and a plurality of memory devices; and the plurality of memory devices coupled with the host CPU cores through respective workload threads and interrupt handlers, wherein the workload threads and interrupt handlers of each of the host CPU cores are configured to be optimized, the host CPU cores are isolated for the optimized workloads threads and interrupt handlers, and the workload threads and interrupt handlers are executed at the host CPU cores coupled thereto.

Abstract: A circuit for enabling the communication of data in a communication link associated with a data communication network is described. The circuit comprises a data generation circuit configured to receive a plurality of data streams and generate an output data stream; a control signal generator configured to generate synchronization headers; a serializer circuit configured to receive the output data stream from the data generation circuit and the synchronization headers from the control signal generator, wherein the serializer circuit generates, at an output, an output data signal having data of the output data stream and the synchronization headers; and a control circuit configured to control the data generation circuit and the control signal generator, wherein the control circuit enables a selection of the synchronization headers of the output data signal to enable channel alignment of the communication link.

Abstract: Techniques and mechanisms to modify packet information in support of on-chip test functionality. In an embodiment, an integrated circuit (IC) chip includes a protocol stack to receive and process packetized information—e.g., where the processing of at least one isochronous timestamp packet (ITP) includes circuitry of the protocol stack replacing non-deterministic data of the ITP with substitute information. A deterministic nature of the substitute information enables the subsequent generation of corresponding signature information which can be used in an evaluation of circuit performance. In another embodiment, the ITP packet is modified at a transaction layer of the protocol stack, and the signature information is determined with an accumulator circuit which is part of another layer of the protocol stack.

Abstract: In accordance with embodiments of the present disclosure, a system may include a rack configured to receive a plurality of server information handling systems, each server information handling system comprising a respective baseboard management controller and a rack manager configured to communicatively couple to each of the respective baseboard management controllers.

Abstract: The present disclosure provides a data accessing method applied to a PCIe storage device. The method comprises: receiving a data reading/writing request sent by a host; calculating a physical storage location of data to be accessed, based on the data reading/writing request, wherein the physical storage location comprises a plurality of PCIe storage devices communicating according to a network protocol; acquiring the data from the plurality of PCIe storage devices based on the network protocol and transferring the data to the host. Also, the disclosure provides a PCIe storage device. With the solution of the disclosure, a PCIe storage device is enabled to access both local and cloud storages, the small-capacity problem with the local storage is addressed and operations of a host's operating system for managing two different types of heterogeneous storages are simplified.

Abstract: The following description is directed to managing a nonvolatile medium. The nonvolatile medium can be organized as a plurality of storage units. In one example, a method can include measuring read latencies for the individual storage units of the nonvolatile medium. A probability distribution of future read latencies for the nonvolatile medium can be estimated based on the measured read latencies for the individual storage units of the nonvolatile medium. Information can be moved from a particular storage unit of the nonvolatile medium to a different storage unit of the nonvolatile medium based on the estimated probability distribution of future read latencies for the nonvolatile medium.

Abstract: A technique for user notification involves receiving an event notification related to an event associated with user notification by a user; providing the event notification from a stored array to a process executed by a processor; using the event notification as a first title used for the process; providing a second title from the stored array to the process; and using the second title to identify the process to the user.

Abstract: A data analysis system to analyze data. The data analysis system includes a data buffer configured to receive data to be analyzed. The data analysis system also includes a state machine lattice. The state machine lattice includes multiple data analysis elements and each data analysis element includes multiple memory cells configured to analyze at least a portion of the data and to output a result of the analysis. The data analysis system includes a buffer interface configured to receive the data from the data buffer and to provide the data to the state machine lattice.

Abstract: An example apparatus includes: a host controller offload capability detector to determine that a media stream offload capability is available in the peripheral interface host controller; a media stream offload arbiter to send a media stream offload request to a media processor manager based on the media stream offload capability and based on a peripheral device being connected to the peripheral interface host controller; and an endpoint mapper to generate an endpoint table entry corresponding to the peripheral device, the endpoint table entry to assign a first communication interface of the peripheral interface host controller to transfer a media stream corresponding to the peripheral device between the media processor and the peripheral interface host controller without the media stream being routed to an application processor that is in circuit with the peripheral interface host controller and in circuit with the media processor.

Abstract: A secure digital format card that includes two interfaces to a processor is provided, comprising a housing, and a processor that includes a secure digital input/output (SDIO) interface, a second interface, and further connections different from the interfaces. A first set and second set of pads are located at the housing, a subset of the first set for communicating with the processor via the SDIO interface. A subset of the second set for communicating with the processor via the second interface, and a further subset of the second set for communicating with the processor via the further connections. The processor is configured to: enable the subset of the second set of pads via the second interface when enable data is received via the one or more further connections, from the further subset of the second set of pads.

Abstract: Provided are a device and computer readable storage medium for programming a memory module to initiate a training mode in which the memory module transmits continuous bit patterns on a side band lane of the bus interface; receiving the bit patterns over the bus interface; determining from the received bit patterns a transition of values in the bit pattern to determine a data eye between the determined transitions of the values; and determining a setting to control a phase interpolator to generate interpolated signals used to sample data within the determined data eye.

Abstract: The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.