Patents Examined by Scott C Sun
  • Patent number: 10909065
    Abstract: A multiprocessor system including at least a first processor and a second processor, includes a storage unit that stores a first program executed by the first processor and a second program executed by the second processor, a memory unit that has a memory region used by the second processor, and a monitoring unit that is connected to the storage unit and the memory unit via a communication line, and, in a case where a program read from the storage unit is the second program, stores the read second program into the memory unit.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: February 2, 2021
    Assignee: FUJI XEROX CO., LTD.
    Inventors: Asahito Shioyasu, Shinho Ikeda, Tomoki Tanihata, Hisashi Noda, Kenta Nomura
  • Patent number: 10904103
    Abstract: An electronic meeting tool and method for communicating arbitrary media content from users at a meeting comprises a node configuration means adapted to operate a display node of a communications network, the display node being coupled to a first display. The node configuration means is adapted to receive user selected arbitrary media content and to control display of the user selected arbitrary media content on the first display. A peripheral device adapted to communicate the user selected arbitrary media content via the communications network is a connection unit comprising a connector adapted to couple to a port of a processing device having a second display, a memory and an operating system, and a transmitter. A program is adapted to obtain user selected arbitrary media content, said program leaving a zero footprint on termination. The user may trigger a transfer of said user selected arbitrary media content to said transmitter.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: January 26, 2021
    Assignee: BARCO N.V.
    Inventors: Koen Simon Herman Beel, Yoav Nir, Filip Josephine Johan Louwet, Guy Coen
  • Patent number: 10891244
    Abstract: An information handling system includes a host configured to write a non-volatile memory express (NVMe) command on a memory submission queue slot. The NVMe command includes a pre-fetch command and a non-completion command. A controller uses the pre-fetch command to monitor read operations, and to place on hold an execution of the monitored read operations and an issuance of an interrupt in response to the non-completion command.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: January 12, 2021
    Assignee: Dell Products, L.P.
    Inventors: Kevin T. Marks, Chandrashekar Nelogal
  • Patent number: 10884689
    Abstract: Described is a technology by which routing of data may be automatically modified based on detected state data of a computing system. For example, user input may be routed from an actuator set to a host computer system when the host computer system is in an online state, or to an auxiliary computing device when the host computer system is offline. State may be determined based on one or more various criteria, such as online or offline, laptop lid position, display orientation, current communication and/or other criteria. The auxiliary display and/or actuator set may be embedded in the host computer system, or each may be separable from it or standalone, such as a remote control or cellular phone.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: January 5, 2021
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Andrew J. Fuller, Niels Van Dongen, Michael George Lenahan
  • Patent number: 10866919
    Abstract: Embodiments of the present disclosure provide an APB (Advanced Peripheral Bus) bus-based SPI (Serial Peripheral Interface) communication device. The device comprises: an APB interface module, an SPI bus interface module, an encryption module, and a decryption module, wherein the encryption module receives plaintext data and a key from a master via the APB interface module, generates, when enabled, ciphertext data according to the plaintext data and the key, and sends the ciphertext data to a slave via the SPI bus interface module; the decryption module receives the ciphertext data from the slave via the SPI bus interface module and receives a key from the master via the APB interface module, generates, when enabled, plaintext data according to the ciphertext data and the key, and sends the plaintext data to the master via the APB interface module. The present disclosure can improve the security of data transmission.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: December 15, 2020
    Inventors: Jun Yang, Jiaqi Xi, Zhiwang Yang, Rui Cai
  • Patent number: 10853279
    Abstract: The invention relates to a system for accessing a shared resource belonging to a hardware platform comprising a plurality of master processing units, each master processing unit being able to exploit a shared resource during an execution of a process, each shared resource having an associated maximum bandwidth. For at least one shared resource, the system includes a counter of a number of data transfers between said master processing unit and said shared resource, and a comparator suitable for comparing the number of transfers to a bandwidth limit, which is a fraction of said maximum bandwidth, associated with said shared resource, and a pacing unit suitable for resetting each counter after a time period of predetermined duration has elapsed.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: December 1, 2020
    Assignee: THALES
    Inventors: Pierrick Lamour, Alexandre Fine
  • Patent number: 10831505
    Abstract: An apparatus and method for data parallel single program multiple data (SPMD) execution. For example, one embodiment of a processor comprises: instruction fetch circuitry to fetch instructions of one or more primary threads; a decoder to decode the instructions to generate uops; a data parallel cluster (DPC) to execute microthreads comprising a subset of the uops, the DPC further comprising: a plurality of execution lanes to perform parallel execution of the microthreads; an instruction decode queue (IDQ) to store the uops prior to execution; and a scheduler to evaluate the microthreads based on associated variables including instruction pointer (IP) values, the scheduler to gang microthreads into fragments for parallel execution on the execution lanes based on the evaluation.
    Type: Grant
    Filed: September 29, 2018
    Date of Patent: November 10, 2020
    Assignee: Intel Corporation
    Inventors: Jonathan Pearce, David Sheffield, Srikanth Srinivasan, Jeffrey Cook, Deborah Marr, Abhijit Davare, Andrey Ayupov
  • Patent number: 10831680
    Abstract: A communication system includes a first communication device and a second communication device communicating with the first communication device. The first communication device includes: a first communication unit receiving, from a first input device, first input information and first information about an attribute of the first input device; and a second communication unit which does not transmit the first information received by the first communication unit to the second communication device but transmits the first input information received by the first communication unit to the second communication device.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: November 10, 2020
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Hiroyuki Hashimoto
  • Patent number: 10824578
    Abstract: Provided is a bitwise writing apparatus for a SOC system. The apparatus includes a slave device interface module, a decoding module and a master device interface module. The slave device interface module is configured to receive a write request sent by a master device interface of a bus controller and send the write request to the decoding module. The decoding module is configured to receive the write request sent by the slave device interface module, decode the write request and send valid information after the decoding to the master device interface module. The master device interface module is configured to receive the valid information sent by the decoding module, read data in a destination address, perform a bitwise operation for the read data to obtain new data, send a write request to a slave device interface of the bus controller and write the obtained new data into a peripheral register corresponding to the destination address.
    Type: Grant
    Filed: December 25, 2018
    Date of Patent: November 3, 2020
    Assignee: C-SKY Microsystems Co., Ltd.
    Inventors: Aiyong Ma, Bo Sun, Baolin Xia, Xianshao Chen
  • Patent number: 10826518
    Abstract: A technology capable of sampling sensor signals in a plurality of channels simultaneously is realized. An input unit is capable of inputting sensor signals from a plurality of sensors, and includes an analog-to-digital (AD) conversion unit which is disposed with respect to each of the plurality of sensors and acquires the sensor signal from each of the sensors and converts the sensor signal into a digital signal, and a timing control unit which controls timing at which a plurality of the AD conversion units acquire the sensor signal for each of the AD conversion units according to a sampling period of each of the plurality of sensors.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: November 3, 2020
    Assignee: OMRON Corporation
    Inventor: Koshiro Shiihara
  • Patent number: 10817436
    Abstract: One embodiment provides a method, including: detecting, using a processor of a host device, that the host device is busy with respect to an impending data transfer to a connectable storage device operatively coupled to the host device; and communicating, to the connectable storage device, data that triggers an indicator of the connectable storage device. Other aspects are described and claimed.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: October 27, 2020
    Assignee: Lenovo (Singapore) Pte. Ltd.
    Inventors: Robert James Kapinos, Russell Speight VanBlon, Timothy Winthrop Kingsbury, Scott Wentao Li
  • Patent number: 10817445
    Abstract: Provided is a semiconductor device and a semiconductor system. A semiconductor device can include a command priority policy manager circuit which generates command priority policy information including a command priority compliance policy for a command directed to a device. A host interface circuit, can be coupled to the command priority policy manager circuit to receive the command priority policy information from the command priority policy manager circuit, where the host interface circuit operable to transmit the command priority policy information via an electrical interface to the device.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: October 27, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-Min Kim, Jeong-Woo Park, Wook Han Jeong, Jin Hwan Choi
  • Patent number: 10817397
    Abstract: Embodiments provide for supporting management of an unrecognized device operating as a component of an IHS (Information Handling System). An unrecognized device operating on the IHS is detected. The unrecognized device is probes for determining properties of the unrecognized device. The unrecognized device is monitored for characteristic communications that are indicative of a type of device. A signature of the unrecognized device is generated based on the probed properties and the monitored communications of the unrecognized. Based on the generated signature, a device pack is created that supports management of the unrecognized device. A device pack may include instructions used by a remote access controller of the IHS for management of the unrecognized device. The created device pack may be generated based on monitoring keys supported by firmware of the unrecognized device. The remote access controller may probe and monitor the unrecognized device.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: October 27, 2020
    Assignee: Dell Products, L.P.
    Inventors: Rakesh Kumar Ayolasomyajula, Sudhir Vittal Shetty, Pushkala Iyer
  • Patent number: 10820442
    Abstract: Examples relate to a modular server architecture that comprises a server chassis, a plurality of independent resource modules releasable attached to the server chassis a memory semantic protocol controller connected to the plurality of independent resource modules. Each one of the resource modules of the plurality of resource modules has a distinct Printed Circuit Board (PCB). The memory semantic media controller is to manage the plurality of independent resource modules.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: October 27, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: John Norton, Hermann Wienchol, David Engler
  • Patent number: 10795832
    Abstract: An electronic meeting tool and method for communicating arbitrary media content from users at a meeting is described. These can include a node configuration means adapted to operate a display node of a communications network, the display node being coupled to a first display. The node configuration means is adapted to receive user selected arbitrary media content and to control display of the user selected arbitrary media content on the first display. At least one peripheral device adapted to communicate the user selected arbitrary media content via the communications network is provided, wherein the peripheral device is a connection unit that includes a connector adapted to couple to a port of a processing device having a second display, a memory and an operating system; and a transmitter for communicating with the communications network.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: October 6, 2020
    Assignee: BARCO N.V.
    Inventors: Koen Simon Herman Beel, Yoav Nir, Filip Josephine Johan Louwet, Guy Coen
  • Patent number: 10795833
    Abstract: A tray for an avionics bay, comprising a body and a recording device rigidly connected to each other in order to reduce the space requirement of acquisition systems on board an aircraft and dedicated to the prediction of failures. The recording device comprises a first input/output port to be connected to the avionics bay, a second input/output port to be connected to an item of electrical equipment, a data bus for routing signals between the first and the second input/output port, a collection member configured for acquiring at least some of the signals routed by the data bus between the first and the second input/output port, and a memory configured to store the signals acquired by the collection member.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: October 6, 2020
    Assignees: AIRBUS SAS, AIRBUS OPERATIONS SAS
    Inventors: Xavier Granier, Alain Lagarrigue, David Cumer
  • Patent number: 10776290
    Abstract: Techniques for processing I/O operations includes: determining whether a current amount of unused physical storage is greater than a threshold; and responsive to determining the current amount of unused physical storage is greater than the threshold, performing normal write processing, and otherwise performing alternative write processing. The alternative write processing includes: initializing a counter; determining whether a physical storage allocation is needed or potentially needed for a write I/O operation; responsive to determining that no physical storage allocation is needed for the write I/O operation, performing the normal write processing. Responsive to determining that a physical storage allocation is needed or potentially needed for the write I/O operation, determining a first amount of one or more credits needed to service the write I/O operation; and responsive to determining the counter does not include at least the first amount of one or more credits, failing the write I/O operation.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: September 15, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Peng Wu, Rong Yu, Jeremy J. O'Hare
  • Patent number: 10762026
    Abstract: An information processing apparatus includes an interface switching circuit including a first hardware interface to which a first device part is coupled; and a first processor including a second hardware interface, wherein the interface switching circuit is configured to block, when hot-removal of the first device part is detected, a signal path between the first hardware interface and the second hardware interface, and cancel, when diagnosis for a second device part newly hot-inserted in the first hardware interface is completed, the blocking of the signal path in response to a result of the diagnosis, and the first processor is configured to detect presence of the second device part from that the first processor transits from a non-responsive state to a responsible state, and execute an initialization process for the second device part.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: September 1, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Naokazu Onda, Hirotoshi Inoue, Hiroaki Watanabe
  • Patent number: 10762003
    Abstract: The present disclosure includes methods, devices, and systems for state change in systems having devices coupled in a chained configuration. A number of embodiments include a host and a number of devices coupled to the host in a chained configuration. The chained configuration includes at least one device that is not directly coupled to the host. The at least one device that is not directly coupled to the host is configured to change from a first communication state to a second communication state responsive to receipt of a command from the host.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: September 1, 2020
    Assignee: Micron Technology, Inc.
    Inventors: William H. Radke, Victor Y. Tsai, James Cooke, Neal A. Galbo, Peter Feeley
  • Patent number: 10754805
    Abstract: A USB adapter includes a first interface connector, a second interface connector, a third interface port and a detecting module. When both of the first interface connector and the second interface connector are plugged into a first electronic device, the USB adapter can acquire higher amount of electricity. Consequently, the sufficient electricity can be provided. Moreover, the detecting module detects a connection status of at least one of the first interface connector and the second interface connector. According to the detecting result, a single default function or plural default functions are enabled.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: August 25, 2020
    Assignee: PRIMAX ELECTRONICS LTD.
    Inventors: Tsung-Wen Hsueh, Yi-Guang Chen