Patents Examined by Scott R. Wilson
  • Patent number: 10658494
    Abstract: Devices and methods of fabricating vertical nanowires on semiconductor devices are provided. One method includes: obtaining an intermediate semiconductor device having a substrate, a first insulator disposed above the substrate, a material layer over the first insulator, a second insulator above the material layer, and a first hardmask; etching a plurality of vertical trenches through the hardmask, the first and second insulators, and the material layer; growing, epitaxially, a set of silicon nanowires from a bottom surface of the plurality of vertical trenches; etching a first set of vertical trenches to expose the material layer; etching a second set of vertical trenches to the substrate; depositing an insulating spacer material on a set of sidewalls of the first and second set of vertical trenches; and forming contacts in the first and second set of vertical trenches.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: May 19, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Dominic J. Schepis, Alexander Reznicek
  • Patent number: 10658501
    Abstract: A high electron mobility transistor (HEMT) includes a channel semiconductor structure including a stack of layers arranged on top of each other in an order of magnitudes of the polarization of materials of the layers to form multiple carrier channels at heterojunctions formed by each pair of layers in the stack. The stack of layers includes a first layer and a second layer. The magnitude of polarization of the first layer is greater than the magnitude of polarization of the second layer arranged in the stack below the first layer, and the width of the first layer is less than the width of the second layer to form a staircase profile of the semiconductor structure. The HEMT includes a source semiconductor structure including a heavily doped semiconductor material, a drain semiconductor structure including the heavily doped semiconductor material. The HEMT includes a source, a drain, and a gate electrodes to modulate the conductivity of the carrier channels.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: May 19, 2020
    Assignee: Mitsubishi Electric Research Laboratories, Inc.
    Inventors: Koon Hoo Teo, Nadim Chowdhury
  • Patent number: 10629756
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a floating substrate; and a capacitor grounded and connected to the floating substrate. A method of manufacturing a semiconductor structure is also provided.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: April 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsiao-Tsung Yen, Yu-Ling Lin, Chin-Wei Kuo, Ho-Hsiang Chen, Chewn-Pu Jou, Min-Chie Jeng
  • Patent number: 10629724
    Abstract: According to one embodiment, a semiconductor device includes first, second and third electrodes, first, second, third, and fourth semiconductor regions, and an insulating portion. The first electrode includes first and second electrode portions. The first semiconductor region includes first, second, and third semiconductor portions. The first semiconductor portion is provided between the first electrode portion and the second electrode. The second semiconductor portion is provided between the second electrode portion and the third electrode. The third semiconductor portion is provided between the first and second semiconductor portions. The second semiconductor region is provided between the first semiconductor portion and the second electrode. The third semiconductor region is positioned between the second semiconductor region and the third electrode. The insulating portion includes first and second insulating regions.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: April 21, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenjiro Uesugi, Shigeya Kimura, Masahiko Kuraguchi
  • Patent number: 10615033
    Abstract: An electronic device having at least a first portion including a metal oxide that is in contact with a second portion including the said metal oxide, the first portion being semiconducting and the second portion being electrically insulating.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: April 7, 2020
    Assignee: Commissariat √† l'√Čnergie Atomique et aux √Čnergies Alternatives
    Inventors: Mohammed Benwadih, Romain Coppard
  • Patent number: 10573649
    Abstract: A semiconductor device includes a substrate, a first well formed in the substrate, a second well formed in the substrate, a first fin formed on the first well, and a second fin formed on the second well. The first well includes a first conductivity type, the second well includes a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other. The substrate includes a first semiconductor material. The first fin and the second fin include the first semiconductor material and a second semiconductor material. A lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. The first semiconductor material in the first fin includes a first concentration, the first semiconductor material in the second fin includes a second concentration, and the second concentration is larger than the first concentration.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: February 25, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Hung Chen, Shih-Hsien Huang, Yu-Ru Yang, Chia-Hsun Tseng, Cheng-Tzung Tsai, Chun-Yuan Wu
  • Patent number: 10553717
    Abstract: A semiconductor device includes a medium voltage MOSFET having a vertical drain drift region between RESURF trenches containing field plates which are electrically coupled to a source electrode of the MOSFET. A split gate with a central opening is disposed above the drain drift region between the RESURF trenches. A two-level LDD region is disposed below the central opening in the split gate. A contact metal stack makes contact with a source region at lateral sides of the triple contact structure, and with a body contact region and the field plates in the RESURF trenches at a bottom surface of the triple contact structure. A perimeter RESURF trench surrounds the MOSFET. A field plate in the perimeter RESURF trench is electrically coupled to the source electrode of the MOSFET. An integrated snubber may be formed in trenches formed concurrently with the RESURF trenches.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: February 4, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Christopher Boguslaw Kocon, Hideaki Kawahara, Simon John Molloy, Satoshi Suzuki, John Manning Savidge Neilson
  • Patent number: 10516110
    Abstract: Subject matter disclosed herein may relate to fabrication of correlated electron materials used, for example, to perform a switching function. In embodiments, processes are described, which may be useful in avoiding formation of a potentially resistive oxide layer at an interfacial surface between a conductive substrate, for example, and a correlated electron material.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: December 24, 2019
    Assignee: ARM Ltd.
    Inventors: Kimberly Gay Reid, Lucian Shifren
  • Patent number: 10505053
    Abstract: An electronic device can include a tunnel structure that includes a first electrode, a second electrode, and tunnel dielectric layer disposed between the electrodes. In a particular embodiment, the tunnel structure may or may not include an intermediate doped region that is at the primary surface, abuts a lightly doped region, and has a second conductivity type opposite from and a dopant concentration greater than the lightly doped region. In another embodiment, the electrodes have opposite conductivity types. In a further embodiment, an electrode can be formed from a portion of a substrate or well region, and the other electrode can be formed over such portion of the substrate or well region.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: December 10, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Thierry Coffi Herve Yao, Gregory James Scott
  • Patent number: 10475807
    Abstract: A method for manufacturing three-dimensional memory, comprising the steps of: forming a stack structure composed of a plurality of first material layers and a plurality of second material layers on a substrate; etching the stack structure to expose the substrate, forming a plurality of first vertical openings; forming a filling layer in each of the first openings; etching the stack structure around each of the first openings to expose the substrate, forming a plurality of second vertical openings; forming a vertical channel layer and a drain in each of the second openings; removing the filling layer by selective etching, re-exposing the first openings; partially or completely removing the second material layers by lateral etching, leaving a plurality of recesses; forming a plurality of gate stack structure in the recesses; forming a plurality of common sources on and/or in the substrate at the bottom of each of the first openings.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: November 12, 2019
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Zongliang Huo, Ming Liu, Lei Jin
  • Patent number: 10475787
    Abstract: A transient voltage suppression (TVS) device, may include: a substrate base formed in a substrate, the substrate base comprising a semiconductor of a first conductivity type; and an epitaxial layer, disposed on the substrate base, on a first side of the substrate, and comprising a semiconductor of a second conductivity type. The epitaxial layer may include: a first portion, the first portion having a first layer thickness; and a second portion, the second portion having a second layer thickness, less than the first layer thickness, wherein the first portion and the second portion are disposed on a first side of the substrate, and wherein the first portion is electrically isolated from the second portion.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: November 12, 2019
    Assignee: LITTELFUSE, INC.
    Inventor: James Allan Peters
  • Patent number: 10461245
    Abstract: According to one embodiment, a method of manufacturing a magnetic memory device, includes forming a stack film including a magnetic layer on an underlying area, forming a hard mask on the stack film, forming a stack structure by etching the stack film using the hard mask as a mask, forming a first protective insulating film on a side surface of the stack structure, and performing an oxidation treatment.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: October 29, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shuichi Tsubata, Masatoshi Yoshikawa, Satoshi Seto, Kazuhiro Tomioka
  • Patent number: 10431613
    Abstract: An image sensor includes a plurality of nanoantennas that satisfy sub-wavelength conditions. Each of the nanoantennas includes a diode and a transistor. Each diode is either a PN diode or a PIN diode.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: October 1, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seunghoon Han, Yibing Michelle Wang
  • Patent number: 10396201
    Abstract: Methods of forming a strained channel device utilizing dislocations disposed in source/drain structures are described. Those methods and structures may include forming a thin silicon germanium material in a source/drain opening of a device comprising silicon, wherein multiple dislocations are formed in the silicon germanium material. A source/drain material may be formed on the thin silicon germanium material, wherein the dislocations induce a tensile strain in a channel region of the device.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: August 27, 2019
    Assignee: Intel Corporation
    Inventors: Michael Jackson, Anand Murthy, Glenn Glass, Saurabh Morarka, Chandra Mohapatra
  • Patent number: 10388741
    Abstract: A first p type semiconductor region is provided between an n type drift region surrounding a drain region and an n type buried region, and a second p type semiconductor region is provided between the first p type semiconductor region and a p type well region surrounding a source region so as to overlap the first p type semiconductor region and the p type well region. Negative input breakdown voltage can be ensured by providing the first p type semiconductor region over the n type buried region. Further, potential difference between the source region and the first p type semiconductor region can be increased and the hole extraction can be performed quickly. Also, a path of hole current flowing via the second p type semiconductor region can be ensured by providing the second p type semiconductor region. Thus, the on-breakdown voltage can be improved.
    Type: Grant
    Filed: January 21, 2017
    Date of Patent: August 20, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Takahiro Mori
  • Patent number: 10361258
    Abstract: Thinned and highly reliable light emitting elements are provided. Further, light emitting devices in which light emitting elements are formed over flexible substrates are manufactured with high yield. One light emitting device includes a flexible substrate, a light emitting element faulted over the flexible substrate, and a resin film covering the light emitting element, and in the light emitting element, an insulating layer serving as a partition has a convex portion and the convex portion is embedded in the resin film, that is, the resin film covers an entire surface of the insulating layer and an entire surface of the second electrode, whereby the light emitting element can be thinned and highly reliable. In addition, a light emitting device can be manufactured with high yield in a manufacturing process thereof.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: July 23, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masahiro Katayama, Shingo Eguchi, Yoshiaki Oikawa, Ami Nakamura, Satoshi Seo, Kaoru Hatano
  • Patent number: 10339444
    Abstract: A neuromorphic electric system includes a network of plural neuron circuits connected in series and in parallel to form plural layers. Each of the plural neuron circuits includes: a soma circuit that stores a charge supplied thereto and outputs a spike signal; and plural synapse circuits that supply a charge to the soma circuit according to a spike signal fed to the synapse circuits, a number of the plural synapse circuits being one more than a number of plural neuron circuits in a prior layer outputting the spike signal to the synapse circuits. One of the plural synapse circuits supplies a charge to the soma circuit in response to receiving a series of pulse signals, and the others of the plural synapse circuits supply a charge to the soma circuit in response to receiving a spike signal from corresponding neuron circuits in the prior layer.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: July 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kohji Hosokawa, Masatoshi Ishii, Atsuya Okazaki, Junka Okazawa, Takayuki Osogami
  • Patent number: 10340373
    Abstract: The present invention relates to the technical field of the power semiconductor device relates to a reverse conducting insulated gate bipolar transistor (RC-IGBT). The RC-IGBT comprises a P-type region, an N-type emitter region, a P-type body contact region, a dielectric trench, a collector region, and an electrical filed cutting-off region. The beneficial effect of the present invention is that, when compared with traditional RC-IGBT, the IGBT of the present invention can eliminate negative resistance effect and effectively improve the performance of forward and reverse conduction.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: July 2, 2019
    Assignee: University of Electronic Science and Technology of China
    Inventors: Xiaorong Luo, Gaoqiang Deng, Kun Zhou, Qing Liu, Linhua Huang, Tao Sun, Bo Zhang
  • Patent number: 10319691
    Abstract: An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: June 11, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Yu-Wei Lin, Sheng-Yu Wu, Yu-Jen Tseng, Tin-Hao Kuo, Chen-Shien Chen
  • Patent number: 10304843
    Abstract: A memory device includes a capacitor, a tunneling-enhanced device, and a transistor. In accordance with an embodiment, capacitor has first and second electrodes wherein the first electrode of the capacitor serves as a control gate of the memory device. The tunneling-enhanced device has a first electrode and a second electrode, wherein the first electrode of the second capacitor serves as an erase gate of the memory device and the second electrode of the tunneling-enhanced device is coupled to the second electrode of the capacitor to form a floating gate. The transistor has a control electrode and a pair of current carrying electrodes, wherein the control electrode of the transistor is directly coupled to the floating gate. In accordance with another embodiment, a method for manufacturing the memory device includes a method for manufacturing the memory device.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: May 28, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Thierry Coffi Herve Yao, Gregory James Scott