Patents Examined by Scott R. Wilson
  • Patent number: 10475807
    Abstract: A method for manufacturing three-dimensional memory, comprising the steps of: forming a stack structure composed of a plurality of first material layers and a plurality of second material layers on a substrate; etching the stack structure to expose the substrate, forming a plurality of first vertical openings; forming a filling layer in each of the first openings; etching the stack structure around each of the first openings to expose the substrate, forming a plurality of second vertical openings; forming a vertical channel layer and a drain in each of the second openings; removing the filling layer by selective etching, re-exposing the first openings; partially or completely removing the second material layers by lateral etching, leaving a plurality of recesses; forming a plurality of gate stack structure in the recesses; forming a plurality of common sources on and/or in the substrate at the bottom of each of the first openings.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: November 12, 2019
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Zongliang Huo, Ming Liu, Lei Jin
  • Patent number: 10475787
    Abstract: A transient voltage suppression (TVS) device, may include: a substrate base formed in a substrate, the substrate base comprising a semiconductor of a first conductivity type; and an epitaxial layer, disposed on the substrate base, on a first side of the substrate, and comprising a semiconductor of a second conductivity type. The epitaxial layer may include: a first portion, the first portion having a first layer thickness; and a second portion, the second portion having a second layer thickness, less than the first layer thickness, wherein the first portion and the second portion are disposed on a first side of the substrate, and wherein the first portion is electrically isolated from the second portion.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: November 12, 2019
    Assignee: LITTELFUSE, INC.
    Inventor: James Allan Peters
  • Patent number: 10461245
    Abstract: According to one embodiment, a method of manufacturing a magnetic memory device, includes forming a stack film including a magnetic layer on an underlying area, forming a hard mask on the stack film, forming a stack structure by etching the stack film using the hard mask as a mask, forming a first protective insulating film on a side surface of the stack structure, and performing an oxidation treatment.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: October 29, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shuichi Tsubata, Masatoshi Yoshikawa, Satoshi Seto, Kazuhiro Tomioka
  • Patent number: 10431613
    Abstract: An image sensor includes a plurality of nanoantennas that satisfy sub-wavelength conditions. Each of the nanoantennas includes a diode and a transistor. Each diode is either a PN diode or a PIN diode.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: October 1, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seunghoon Han, Yibing Michelle Wang
  • Patent number: 10396201
    Abstract: Methods of forming a strained channel device utilizing dislocations disposed in source/drain structures are described. Those methods and structures may include forming a thin silicon germanium material in a source/drain opening of a device comprising silicon, wherein multiple dislocations are formed in the silicon germanium material. A source/drain material may be formed on the thin silicon germanium material, wherein the dislocations induce a tensile strain in a channel region of the device.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: August 27, 2019
    Assignee: Intel Corporation
    Inventors: Michael Jackson, Anand Murthy, Glenn Glass, Saurabh Morarka, Chandra Mohapatra
  • Patent number: 10388741
    Abstract: A first p type semiconductor region is provided between an n type drift region surrounding a drain region and an n type buried region, and a second p type semiconductor region is provided between the first p type semiconductor region and a p type well region surrounding a source region so as to overlap the first p type semiconductor region and the p type well region. Negative input breakdown voltage can be ensured by providing the first p type semiconductor region over the n type buried region. Further, potential difference between the source region and the first p type semiconductor region can be increased and the hole extraction can be performed quickly. Also, a path of hole current flowing via the second p type semiconductor region can be ensured by providing the second p type semiconductor region. Thus, the on-breakdown voltage can be improved.
    Type: Grant
    Filed: January 21, 2017
    Date of Patent: August 20, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Takahiro Mori
  • Patent number: 10361258
    Abstract: Thinned and highly reliable light emitting elements are provided. Further, light emitting devices in which light emitting elements are formed over flexible substrates are manufactured with high yield. One light emitting device includes a flexible substrate, a light emitting element faulted over the flexible substrate, and a resin film covering the light emitting element, and in the light emitting element, an insulating layer serving as a partition has a convex portion and the convex portion is embedded in the resin film, that is, the resin film covers an entire surface of the insulating layer and an entire surface of the second electrode, whereby the light emitting element can be thinned and highly reliable. In addition, a light emitting device can be manufactured with high yield in a manufacturing process thereof.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: July 23, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masahiro Katayama, Shingo Eguchi, Yoshiaki Oikawa, Ami Nakamura, Satoshi Seo, Kaoru Hatano
  • Patent number: 10340373
    Abstract: The present invention relates to the technical field of the power semiconductor device relates to a reverse conducting insulated gate bipolar transistor (RC-IGBT). The RC-IGBT comprises a P-type region, an N-type emitter region, a P-type body contact region, a dielectric trench, a collector region, and an electrical filed cutting-off region. The beneficial effect of the present invention is that, when compared with traditional RC-IGBT, the IGBT of the present invention can eliminate negative resistance effect and effectively improve the performance of forward and reverse conduction.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: July 2, 2019
    Assignee: University of Electronic Science and Technology of China
    Inventors: Xiaorong Luo, Gaoqiang Deng, Kun Zhou, Qing Liu, Linhua Huang, Tao Sun, Bo Zhang
  • Patent number: 10339444
    Abstract: A neuromorphic electric system includes a network of plural neuron circuits connected in series and in parallel to form plural layers. Each of the plural neuron circuits includes: a soma circuit that stores a charge supplied thereto and outputs a spike signal; and plural synapse circuits that supply a charge to the soma circuit according to a spike signal fed to the synapse circuits, a number of the plural synapse circuits being one more than a number of plural neuron circuits in a prior layer outputting the spike signal to the synapse circuits. One of the plural synapse circuits supplies a charge to the soma circuit in response to receiving a series of pulse signals, and the others of the plural synapse circuits supply a charge to the soma circuit in response to receiving a spike signal from corresponding neuron circuits in the prior layer.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: July 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kohji Hosokawa, Masatoshi Ishii, Atsuya Okazaki, Junka Okazawa, Takayuki Osogami
  • Patent number: 10319691
    Abstract: An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: June 11, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Yu-Wei Lin, Sheng-Yu Wu, Yu-Jen Tseng, Tin-Hao Kuo, Chen-Shien Chen
  • Patent number: 10304843
    Abstract: A memory device includes a capacitor, a tunneling-enhanced device, and a transistor. In accordance with an embodiment, capacitor has first and second electrodes wherein the first electrode of the capacitor serves as a control gate of the memory device. The tunneling-enhanced device has a first electrode and a second electrode, wherein the first electrode of the second capacitor serves as an erase gate of the memory device and the second electrode of the tunneling-enhanced device is coupled to the second electrode of the capacitor to form a floating gate. The transistor has a control electrode and a pair of current carrying electrodes, wherein the control electrode of the transistor is directly coupled to the floating gate. In accordance with another embodiment, a method for manufacturing the memory device includes a method for manufacturing the memory device.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: May 28, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Thierry Coffi Herve Yao, Gregory James Scott
  • Patent number: 10289950
    Abstract: A neuromorphic electric system includes a network of plural neuron circuits connected in series and in parallel to form plural layers. Each of the plural neuron circuits includes: a soma circuit that stores a charge supplied thereto and outputs a spike signal; and plural synapse circuits that supply a charge to the soma circuit according to a spike signal fed to the synapse circuits, a number of the plural synapse circuits being one more than a number of plural neuron circuits in a prior layer outputting the spike signal to the synapse circuits. One of the plural synapse circuits supplies a charge to the soma circuit in response to receiving a series of pulse signals, and the others of the plural synapse circuits supply a charge to the soma circuit in response to receiving a spike signal from corresponding neuron circuits in the prior layer.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: May 14, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kohji Hosokawa, Masatoshi Ishii, Atsuya Okazaki, Junka Okazawa, Takayuki Osogami
  • Patent number: 10259701
    Abstract: A MEMS device and a method to manufacture a MEMS device are disclosed. An embodiment includes forming trenches in a first main surface of a substrate, forming conductive fingers by forming a conductive material in the trenches and forming an opening from a second main surface of the substrate thereby exposing the conductive fingers, the second main surface opposite the first main surface.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: April 16, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventor: Alfons Dehe
  • Patent number: 10249535
    Abstract: A method of forming a logic or memory cell with less than or equal to 0 nm of TS extending past the active fins and the resulting device are provided. Embodiments include forming gates across pairs of fins on a substrate; forming pairs of RSD between the gates on the fins; forming a planar SAC cap on each of the gates; forming a metal layer over the substrate coplanar with the SACs; forming a TS structure in the metal layer over the fins, the TS structure formed over the pairs of RSD, each upper portion having a width equal to or less than an overall width of a pair of fins; forming spacers on opposite sides of the upper portions; removing the metal layer between adjacent spacers; forming an ILD over the substrate; and forming a CA on each upper portion and a CB on a gate through the ILD.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: April 2, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Daniel Chanemougame, Lars Liebmann, Nigel Cave
  • Patent number: 10186635
    Abstract: A method of forming a vertical III-nitride based light emitting diode structure 5 and a vertical III-nitride based light emitting diode structure can be provided. The method comprises forming a III-nitride based light emitting structure on a silicon-oninsulator (SOI) substrate; forming a metal-based electrode structure on the III-nitride based light emitting structure; and removing the SOI substrate by a layer transfer process such that the metal-based electrode structure functions as a metal-based 10 substrate of the light emitting structure.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: January 22, 2019
    Assignee: AGENCY FOR SCIENCE TECHNOLOGY AND RESEARCH
    Inventors: Tripathy Sudhiranjan, Lin Vivian Kaixin, Teo Siew Lang, Dolmanan Surani Bin
  • Patent number: 10167566
    Abstract: A substrate (5) in which a surface of an aluminum base (10) other than a surface on which an insulating thin film layer (17) is formed is covered with a protective layer (19) which is an aluminum anodic oxide film.
    Type: Grant
    Filed: July 25, 2014
    Date of Patent: January 1, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Masahiro Konishi, Shin Itoh
  • Patent number: 10153378
    Abstract: Provided is a structure of a transistor, which enables a so-called normally-off switching element, and a manufacturing method thereof. Provided is a structure of a semiconductor device which achieves high-speed response and high-speed operation by improving on characteristics of a transistor, and a manufacturing method thereof. Provided is a highly reliable semiconductor device. In the transistor in which a semiconductor layer, source and drain electrode layers, a gate insulating layer, and a gate electrode layer are stacked in that order. As the semiconductor layer, an oxide semiconductor layer which contains at least four kinds of elements of indium, gallium, zinc, and oxygen, and has a composition ratio (atomic percentage) of indium as twice or more as a composition ratio of gallium and a composition ratio of zinc, is used.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: December 11, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masahiro Takahashi, Tatsuya Honda, Takehisa Hatano
  • Patent number: 10109774
    Abstract: Pre-formed wavelength conversion elements are attached to light emitting elements and are shaped to reduce repeated occurrences of total internal reflection. The sides of the shaped elements may be sloped or otherwise shaped so as to introduce a change in the angle of incidence of reflected light upon the light extraction surface of the wavelength conversion element. The pre-formed wavelength conversion elements may be configured to extend over an array of light emitting elements, with features between the light emitting elements that are shaped to reduce repeated occurrences of total internal reflection.
    Type: Grant
    Filed: August 12, 2014
    Date of Patent: October 23, 2018
    Assignee: Lumileds LLC
    Inventors: Clarisse Mazuir, Qingwei Mo, Mei-Ling Kuo, Lin Li, Oleg Borisovich Shchekin
  • Patent number: 10096750
    Abstract: A display device include a substrate including a wiring electrode; an adhesive layer disposed on the substrate; a plurality of semiconductor light emitting devices adhered to the adhesive layer, and electrically connected to the wiring electrode; and a phosphor layer disposed to cover the plurality of semiconductor light emitting devices. Further, the phosphor layer includes a plurality of phosphor portions for converting a wavelength of light, and a plurality of partition wall portions formed between the plurality of phosphor portions, and the plurality of partition wall portions are sequentially disposed between the phosphor portions along a first direction and a second direction crossing each other, respectively, and at least one of the sequentially disposed partition wall portions overlaps with at least one of the plurality of semiconductor light emitting devices.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: October 9, 2018
    Assignee: LG ELECTRONICS INC.
    Inventors: Hwanjoon Choi, Yonghan Lee, Sungjin Park
  • Patent number: 10069045
    Abstract: A method of manufacturing a light emitting device including: forming a supporting body on a mounting surface of each of semiconductor light emitting elements; arranging the semiconductor light emitting elements to be spaced apart from each other by a predetermined distance; and forming a wavelength conversion layer to continuously cover an upper surface and side surfaces of at least one of the semiconductor light emitting elements. The forming the wavelength conversion layer includes spraying a slurry provided by mixing particles of a wavelength conversion member and a thermosetting resin in a solvent onto the upper surface and the side surfaces of the semiconductor light emitting element, so that a thickness of the wavelength conversion layer at a lower portion of the side surfaces of the supporting body is smaller than the thickness on the upper surface and the side surfaces of the semiconductor light emitting element.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: September 4, 2018
    Assignee: NICHIA CORPORATION
    Inventors: Takeshi Ikegami, Tadao Hayashi, Hiroto Tamaki